SMTS-Design Verification Engineer: PCIE / CXL Focused

Tsavorite Scalable Intelligence; Bengaluru; On-site; INR 10,516,000 - 16,252,000; Full time

Job summary

Tsavorite Scalable Intelligence is seeking a senior verification engineer to work on high‑performance PCIe/CXL controllers and multi‑controller sub-systems at block and SoC levels.

You will develop test plans, DV environments, and checkers, execute regressive tests, and support post‑Si bring‑up. The role demands deep experience in UVM, C/C++, and industry tools, with strong architecture knowledge and test coverage.

Qualifications

• Bachelor's or Master's degree in Electrical/Electronics Engineering/Science is required.
• 11+ years of relevant verification experience is needed.
• Strong knowledge of PCIE and CXL alongside PIPE and serdes is essential.

Responsibilities

• Partner with Architects and RTL Design to understand system requirements.
• Develop verification plans and testbenches for IP/Sub-system or domain.
• Create DV environments with bus functional models and checkers.
• Execute tests, run regressions, debug failures, and track coverage.
• Support post-Si bring-up and debug activities.
• Report DV progress with metrics and bug tracking.

Skills

UVM

C/C++

Test planning

DV environment

Assertion-based

Education

Electrical Eng

Electronics Eng

Science

Tools

Questa

VCS

Visualizer

Job description

Founded in 2023,by Industry veterans HQ in California,US

Company Description

We are looking for exceptional talent and leadership to join , the world’s first company developing Agentic Silicon for powering the future of AI.

Founded in 2023, our team consists of 90+ highly skilled engineers from leading companies such as Intel, Marvell, Nvidia, Qualcomm, Cisco, AMD, Apple etc. We have deep customer engagements across America, Europe, and Asia, and demonstrated functional prototypes to prove our concept and vision.

Job Description

In this role you will be working on high performance server class PCIe/CXL controllers and multi-controller sub-systems at block and SoC level. The task list includes, but is not limited to, testplan development, env development, checker/scoreboard development, test execution and analysis at sub-system, chiplet and multi-chiplet level

Roles And Responsibilities

• Partner with Architects and RTL Design team to grasp high-level system requirements and specifications.
• Formulate comprehensive test and coverage plans to match the Architecture and micro-architecture.
• Develop the verification environment and reusable bus functional models, stimulus, checkers, assertions, trackers, and coverage metrics.
• Create verification plans and develop testbenches tailored to assigned IP/Sub-system or functional domain.
• Execute verification plans, including tasks such as design bring-up, setting up the DV environment, running regressions for feature validation, and debugging test failures.
• Support post-Si bring-up and debug activities.
• Track and communicate progress in the DV process by using key metrics like testplan status, bug tracking and coverage reports.

Requirements

• Bachelor’s or Master’s degree in Electrical/Electronics Engineering/Science with 11+years of relevant experience
• Strong Architecture domain knowledge in latest generation of PCIE and CXL protocols, PIPE, serdes.
• Must have strong expertise with SV/UVM methodology and/or C/C++ based verification with 5yrs+ hands-on experience in IP/sub-system and/or SoC level verification
• Hands on experience and expertise with industry standard verification tools for simulation and debug (Questa/VCS, Visualizer)
• Experience using random stimulus along with functional coverage and assertion-based verification methodologies a must.

Preferred Qualifications:

• Experience in development of UVM based verification environments from scratch.
• Hands on expertise with PCIE/CXL controller and sub-system verification as root/host and end-point/client
• Hands on expertise and protocol knowledge in any of: APB/AXI protocols , PCIE/CXL protocols and compliance testing