Physical Design (PD) Engineer

Ad Astra Consultants; Bengaluru; On-site; INR 900,000 - 1,300,000; Full time

Job summary

Ad Astra Consultants in Bengaluru, India, seeks an STA engineer to develop and maintain robust timing constraints, perform block-level and full-chip STA, and drive timing closure across complex MMMC scenarios.

You will own RTL synthesis with constraint setup, QoR optimization, and netlist quality checks, while debugging timing issues and collaborating with RTL, PD, and architecture teams. Mentorship and strong communication are essential.

Qualifications

• 3–5 years hands-on experience in STA, constraints development, and synthesis.
• Strong STA fundamentals (setup/hold, OCV/AOCV/POCV, SI, derates).
• Expertise in PrimeTime or Cadence Tempus for timing analysis.
• Solid RTL to GDSII design flow understanding and SoC timing architecture.

Responsibilities

• Develop, review, and maintain robust SDC constraints (clocks, I/O, generated clocks, timing exceptions).
• Perform block level and full chip STA and ensure timing closure across MMMC scenarios.
• Own RTL synthesis with constraint setup, QoR optimization, and netlist checks.
• Analyze timing violations, identify root causes, and collaborate with RTL/PD/architecture teams.
• Validate constraints across synthesis, PnR, and sign-off stages for consistency.
• Drive timing ECOs and support post-route optimization to achieve sign-off timing.
• Generate timing reports, summarize risks, and propose optimization strategies.
• Mentor junior engineers on STA, SDC, and synthesis best practices.

Skills

STA fundamentals

PrimeTime/Tempus

RTL to GDSII flow

Synthesis debugging

Cross-functional collaboration

Timing closure

Tools

PrimeTime

Tempus

Design Compiler

Fusion Compiler

Genus

Job description

• Develop, review, and maintain robust SDC constraints (clocks, I/O, generated clocks, timing exceptions).
• Perform block level and full chip STA using PrimeTime/Tempus and ensure timing closure across all MMMC scenarios.
• Own RTL synthesis (Design Compiler/Fusion Compiler/Genus), including constraint setup, QoR optimization, and netlist quality checks.
• Analyze timing violations, identify root causes, and collaborate with RTL, PD, and architecture teams to resolve issues.
• Validate constraints across synthesis, PnR, and sign off stages to ensure correctness and consistency.
• Drive timing ECOs and support post route optimization to achieve sign off timing.
• Generate timing reports, summarize key risks, and propose optimization strategies.
• Mentor junior engineers on STA, SDC, and synthesis best practices.

Required Skills & Experience:

• 3 - 5 years of hands on experience in STA, constraints development, and synthesis.
• Strong understanding of STA fundamentals (setup/hold, OCV/AOCV/POCV, SI, derates, CPPR).
• Expertise in Synopsys PrimeTime or Cadence Tempus for timing analysis.
• Strong synthesis experience with Design Compiler, Fusion Compiler, or Cadence Genus.
• Solid understanding of RTL to GDSII design flow and SoC timing architecture.
• Proven ability to independently debug complex timing/synthesis issues and drive closure.
• Excellent communication and cross functional collaboration skills.