Staff Engineer - STA

BITSILICA; Bengaluru; On-site; INR 3,500,000 - 6,500,000; Full time

Job summary

BITSILICA in Bengaluru, India seeks an experienced Static Timing Analysis (STA) Engineer to lead timing sign-off for complex SoC designs. You will own block and full-chip STA, drive timing closure, and develop timing constraints in collaboration with PD, RTL, and Architecture teams to ensure successful tape-out.

The role requires hands-on experience with Synopsys PrimeTime, debugging setup/hold violations, and a deep understanding of clocking architectures and CDC concepts in advanced technology

Qualifications

• 10+ years of STA experience required.
• Hands-on in timing closure and sign-off for complex SoCs.
• Proven ability to develop and validate timing constraints (SDC).
• Strong debugging skills for setup/hold violations and timing paths.
• Experience collaborating with Physical Design, RTL, and Architecture teams.

Responsibilities

• Perform block and full-chip Static Timing Analysis for complex SoC designs.
• Develop and validate timing constraints (SDC).
• Drive timing closure across corners and modes.
• Analyze and debug setup/hold violations.
• Work with Physical Design, RTL, and Architecture teams.
• Support ECO implementation for timing fixes.
• Handle timing sign-off for tape-out.
• Perform clock tree and timing path analysis.
• Strong expertise in STA and PrimeTime.
• Understand clocking architecture and CDC concepts.
• Exposure to advanced technology nodes.
• Good understanding of Physical Design flow.

Skills

STA experience

Timing Closure

Timing Constraints

Clock Tree

Setup/Hold

ECO/Sign-off

PD/RTL Collab

Timing Sign-off

SoC Design

PrimeTime

Tools

Synopsys PrimeTime

Job description

Notice Period: Immediate to 30 Days Preferred

We are looking for an experienced Static Timing Analysis (STA) Engineer with strong expertise in timing sign-off for complex SoC designs. The candidate should have hands‑on experience in timing closure, constraints development, and working closely with PD and RTL teams to achieve design closure.

• Perform block and full-chip Static Timing Analysis for complex SoC designs
• Develop and validate timing constraints (SDC)
• Drive timing closure across different corners and modes
• Analyze and debug setup/hold violations
• Work closely with Physical Design, RTL, and Architecture teams
• Support ECO implementation for timing fixes
• Handle timing sign-off for tape‑out
• Perform clock tree and timing path analysis
• Strong expertise in Static Timing Analysis (STA)
• Hands‑on experience with Synopsys PrimeTime
• Strong understanding of timing constraints (SDC)
• Experience in timing closure and sign‑off
• Understanding of clocking architecture and CDC concepts
• Exposure to advanced technology nodes
• Good understanding of Physical Design flow

Good to Have

• Experience with CPU/GPU or high‑performance SoC designs
• Knowledge of Low Power (UPF/CPF)
• Exposure to Synthesis and PD flow
• Experience in ECO and sign‑off flows
• 10+ years of experience in STA / Timing Analysis
• Strong debugging and problem-solving skills
• Ability to work independently and drive timing closure