Physical Design Engineer (Synthesis)

LanceSoft, Inc.; Bengaluru; On-site; INR 3,000,000 - 6,000,000; Full time

Job summary

LanceSoft, Inc. in Bengaluru seeks an experienced Lead Synthesis & STA Engineer to drive RTL synthesis, full-chip STA, and timing closure for complex SoCs. You will own critical timing flows, push design improvements, and collaborate with RTL, Physical Design, and DFT teams to resolve timing issues.

Applicants must be proficient with Cadence Genus and Tempus, have deep SDC knowledge, timing constraints, setup/hold analysis, and a proven record of PPA optimization across large-scale platforms.

Qualifications

• 8+ years of experience in RTL Synthesis and Static Timing Analysis.
• Hands-on experience with Cadence Genus and Tempus.
• Expertise in full-chip STA, timing constraints, and timing closure.
• Strong knowledge of SDC, setup/hold analysis, and timing optimization.

Responsibilities

• Lead RTL synthesis, timing analysis, and optimization for complex SoC designs.
• Perform full-chip STA, timing closure, and setup/hold violation analysis.
• Drive timing, power, and area (PPA) optimization.
• Work on SDC constraints development, validation, and timing exceptions.
• Collaborate with RTL, Physical Design, and DFT teams to resolve timing issues.
• Lead design reviews, debug critical paths, and drive closure activities.

Skills

RTL Synthesis

Static Timing Analysis

Timing closure

SDC

PPA optimization

SoC design flows

Cadence Genus

Cadence Tempus

Tools

Cadence Genus

Cadence Tempus

Job description

We are looking for an experienced Lead Synthesis & STA Engineer with strong expertise in RTL synthesis, full-chip Static Timing Analysis (STA), and Cadence EDA tools.

Key Responsibilities

• Lead RTL synthesis, timing analysis, and optimization for complex SoC designs.
• Perform full-chip STA, timing closure, and setup/hold violation analysis.
• Drive timing, power, and area (PPA) optimization.
• Work on SDC constraints development, validation, and timing exceptions.
• Collaborate with RTL, Physical Design, and DFT teams to resolve timing issues.
• Lead design reviews, debug critical paths, and drive closure activities.

Must-Have Skills

• 8+ years of experience in RTL Synthesis and Static Timing Analysis.
• Strong hands-on experience with Cadence Genus and Tempus.
• Expertise in full-chip STA, timing constraints, and timing closure.
• Strong knowledge of SDC, setup/hold analysis, and timing optimization.
• Experience with PPA optimization and advanced SoC design flows.