Physical Design Lead (Full Chip)

7Rays Semiconductors; Delhi; On-site; INR 3,500,000 - 5,500,000; Full time

Job summary

7Rays Semiconductors is seeking a Senior Physical Design Engineer in Noida with 7+ years in physical design and a strong background in SoC floorplanning using Innovus. You will lead IO ring creation, floorplan strategies, and sign-off activities for next-gen process technologies.

The ideal candidate has deep scripting experience (TCL/Perl/Makefiles), hierarchical design knowledge, and a proven track record in P&R flows, packaging interactions, and DV/PV clean-up for flows across large teams.

Qualifications

• Minimum 7 years in Physical Design with SoC floorplanning experience.
• Expert in Innovus-based floorplanning and IO ring implementation.
• Knowledge of ESD, latch-up and foundry placement requirements.
• Experience in hierarchical partitioning, HM/tiles push-down methods.
• PV sign-off experience including metal-fill, DFM rules.

Skills

Physical Design

SoC Floorplanning

IO Ring Design

ESD & Latch-up

Hierarchical Design

P&R Methodologies

Analog Placement

RDL & Packaging

PV Cleanup

Scripting

Flow Automation

TCL/Perl Scripting

Sign-off Issues

Problem Solving

Education

Bachelor's degree in Electrical/Electronics/Computer Engineering

Tools

Innovus

Job description

At 7Rays Semiconductors (), we provide end-to-end VLSI design solutions to help our clients achieve execution excellence. Our team of experts specializes in architecture, RTL design, verification, validation, physical design, implementation, and post-silicon validation using the latest technologies and methodologies

We work closely with our clients, building effective partnerships to deliver high-quality solutions tailored to their needs. With a proven track record of successful projects, we are committed to excellence and innovation in semiconductor design.

Job: Senior Physical Design Engineer

Experience: 7–12+ years

Location: Noida

• 7+ years experience in Physical Design
• Extensive expertise in Floorplanning for SoC using Innovus
• Must have a knowledge and implementation strategies to create an IO ring in accordance design specification
• Have a deep knowledge on ESD, latch-up etc for foundary requirements and placement strategies
• Should have a higherarchial design implementation knowledge which include partitions/HMs/tiles push down to each core/tile
• PG creation and push down methodologies knowledge and implementation
• Should have a knowledge on Analog components and their requirements in placements according to design specifications
• RDL knowledge and working with packaging is a must for SoC floorplan designer
• PV clean-up on floorplan and self derive in all the sign-off including Physical Verification, ESD and foundry/Analog requirements
• Deep scripting knowledge is essential
• Should be capable of providing solutions to flow, tool, design setup elated issues proactively at large team level
• Strong TCL/Perl/Makefile scripting knowledge as well as experience developing complex algorithms, managing, and regressing P&R flows.
• Familiar with sign-off issues (metal-fill, spare-cells, DFM rules, boundary-cells, etc.) for the latest generations of process technologies
• Good problem-solving capabilities, proactive, hardworking with strong interpersonal skills
• Bachelors Degree in Electrical, Electronics or Computer Engineering