Physical Design Lead (Full Chip)

7Rays Semiconductors; Bengaluru; On-site; INR 4,000,000 - 7,500,000; Full time

Job summary

7Rays Semiconductors is seeking a Coherency Senior Physical Design Engineer in Bangalore. The role demands 7+ years in Physical Design, with deep experience in floorplanning for SoCs using Innovus and IO ring creation per design specs.

You will drive PV sign-off, ESD/foundry considerations, and flow improvements. Strong scripting and hierarchical design skills are essential for proactive problem solving.

Qualifications

• 7+ years experience in Physical Design.
• Extensive expertise in Floorplanning for SoC using Innovus.
• Knowledge to create an IO ring in accordance with design spec.
• Deep knowledge on ESD, latch-up and foundry requirements.
• Hierarchical design implementation incl. partitions/tiles push down to cores.
• PG creation and push down methodologies knowledge.
• Analog components requirements in placements per spec.
• RDL and packaging is a must for SoC floorplan designer.
• PV clean-up on floorplan and sign-off incl. ESD and foundry/Analog requirements.
• Strong TCL/Perl/Makefile scripting and complex algorithm development.

Responsibilities

• Develop and optimize floorplans for high‑end SoCs.
• Create IO rings per design specifications with reliable routing.
• Coordinate sign-off readiness including PV, ESD, and foundry constraints.
• Improve design flows, tool setup, and debugging across the team.
• Apply knowledge of analog blocks and placement strategies in layouts.
• Work with packaging teams on RDL and package integration.

Skills

Physical Design

Floorplanning SoC

Innovus

IO Ring Design

Scripting TCL/Perl

Analog/Foundry Rules

RDL & Packaging

PV Sign-off

Partitioning/ Tiles

Flow/Tool Debug

DFM & Metal-fill

Education

Bachelor's Degree in Electrical, Electronics or Computer Engineering

Tools

Innovus

Job description

At 7Rays Semiconductors (), we provide end-to-end VLSI design solutions to help our clients achieve execution excellence. Our team of experts specializes in architecture, RTL design, verification, validation, physical design, implementation, and post-silicon validation using the latest technologies and methodologies

We work closely with our clients, building effective partnerships to deliver high-quality solutions tailored to their needs. With a proven track record of successful projects, we are committed to excellence and innovation in semiconductor design.

Job: Coherency Senior Physical Design Engineer

Experience: 7–12+ years

Location: Bangalore

• 7+ years experience in Physical Design
• Extensive expertise in Floorplanning for SoC using Innovus
• Must have a knowledge and implementation strategies to create an IO ring in accordance design specification
• Have a deep knowledge on ESD, latch-up etc for foundary requirements and placement strategies
• Should have a higherarchial design implementation knowledge which include partitions/HMs/tiles push down to each core/tile
• PG creation and push down methodologies knowledge and implementation
• Should have a knowledge on Analog components and their requirements in placements according to design specifications
• RDL knowledge and working with packaging is a must for SoC floorplan designer
• PV clean-up on floorplan and self derive in all the sign-off including Physical Verification, ESD and foundry/Analog requirements
• Deep scripting knowledge is essential
• Should be capable of providing solutions to flow, tool, design setup elated issues proactively at large team level
• Strong TCL/Perl/Makefile scripting knowledge as well as experience developing complex algorithms, managing, and regressing P&R flows.
• Familiar with sign-off issues (metal-fill, spare-cells, DFM rules, boundary-cells, etc.) for the latest generations of process technologies
• Good problem-solving capabilities, proactive, hardworking with strong interpersonal skills
• Bachelors Degree in Electrical, Electronics or Computer Engineering