Principal Physical Design Engineer

NXP Semiconductors; Bengaluru; On-site; INR 4,200,000 - 6,800,000; Full time

Job summary

NXP Semiconductors is seeking a Principal Physical Design Engineer for AI NPU in India. The role leads physical design from RTL synthesis to timing convergence, collaborates with PD verification, power integrity and DFT teams, and drives automation within the PD flow.

The ideal candidate has 8+ years of digital PD experience on complex SoCs/ASICs, strong EDA tool proficiency, and deep knowledge of STA, floorplanning, and sub-micron processes. Excellent communication and teamwork are essential.

Qualifications

• Bachelor's or Master's degree in VLSI or Electronics Engineering or a related field.
• Minimum 8 years of experience in digital physical design of complex SoCs or ASICs.
• Proficiency with industry-standard EDA tools for physical design (Cadence Innovus/Genus/Tempus, Synopsys Fusion Compiler/PrimeTime, Mentor Calibre).
• Strong understanding of floorplanning, placement, routing, clock tree synthesis, and physical verification.
• Solid knowledge of Static Timing Analysis (STA) and timing closure techniques.
• Experience with scripting languages (Tcl, Perl, Python).
• Familiarity with deep sub-micron process technologies.
• Good communication and collaborative skills.

Responsibilities

• Execute physical design activities including floorplanning, power planning, place and route, clock tree synthesis, and STA.
• Collaborate with physical verification (DRC, LVS, Antenna) and resolve issues.
• Collaborate with power integrity analysis (IR drop, EM) and optimize designs for power efficiency.
• Coordinate with design, verification, and DFT teams to ensure integration and milestones.
• Analyze and resolve timing, area, and power issues.
• Develop scripts for automation and efficiency in PD flow.
• Contribute to PD methodology improvements and documentation.

Skills

Digital design

Physical design

Scripting (Tcl/Perl/Python)

STA/timing closure

Team collaboration

Education

Bachelor's or Master's in VLSI/Electronics

Tools

Cadence Innovus/Genus/Tempus

Synopsys Fusion Compiler/PrimeTime

Mentor Calibre

Job description

## Principal Physical Design EngineerApply: Hyderabad: Bangalore: Noida: Full time: Posted Today: R-10063208**Job Summary:**We are seeking a highly experienced Lead PD Engineer for AI NPU to lead and contribute to the physical design and implementation of complex, high-performance semiconductor integrated circuits. The individual is responsible from RTL synthesis, Floor planning, Placement, CTS, Routing, Timing convergence (STA). The individual contributes to problem solving related to physical design. Contributes to define best Physical design strategy per technology node.**Job Responsibilities** \\* Execute physical design activities including floorplanning, power planning, place and route, clock tree synthesis, and static timing analysis (STA). \\* Collaborate with physical verification (DRC, LVS, Antenna) and resolve related issues. \\* Collaborate with power integrity analysis (IR drop, EM) and optimize designs for power efficiency. \\* Collaborate with design, verification, and DFT teams to ensure seamless integration and achieve project milestones. \\* Analyze and resolve design issues related to timing, area, and power. \\* Develop and maintain scripts for automation and efficiency improvements in the physical design flow. \\* Contribute to the continuous improvement of physical design methodologies and flows. \\* Generate comprehensive reports and documentation of design implementation.**Job Qualifications** \\* Bachelor's or Master's degree in VLSI or Electronics Engineering or a related field. \\* Minimum 8 years of experience in digital physical design of complex SoCs or ASICs. \\* Proficiency with industry-standard EDA tools for physical design (e.g., Cadence Innovus/Genus/Tempus or Synopsys Fusion Compiler/PrimeTime, Mentor Calibre). \\* Solid understanding and experience of physical design concepts including floorplanning, placement, routing, clock tree synthesis, and physical verification. \\* Strong knowledge of Static Timing Analysis (STA) and timing closure techniques. \\* Experience with scripting languages such as Tcl, Perl, or Python. \\* Familiarity with deep sub-micron process technologies. \\* Good understanding of VLSI design principles and semiconductor physics. \\* Excellent problem-solving skills and attention to detail. \\* Ability to work effectively in a collaborative team environment. \\* Good communication skills, both written and verbal.