Lead physical design engineer

Siliconus Technologies Pvt Ltd; Bengaluru; On-site; INR 4,000,000 - 6,000,000; Full time

Job summary

Siliconus Technologies Private Limited is seeking an experienced Lead Physical Design Engineer to lead and manage PD activities across block-level and full-chip projects in Bengaluru, India. The candidate will drive end-to-end RTL-to-GDSII flows, timing closure, signoff, and customer interactions with strong leadership skills.

The role requires 7+ years of PD experience, hands-on expertise in advanced nodes, and proficiency with Cadence Innovus, Tempus, and Synopsys tools.

Qualifications

• Bachelor's or Master’s degree in Electronics/ECE/VLSI or related engineering discipline.
• 7+ years of relevant Physical Design experience.
• Proven experience leading Physical Design teams/projects.
• Strong block-level and/or full-chip implementation experience.
• Multiple tapeout experience is highly preferred.

Responsibilities

• Lead the end-to-end Physical Design flow from netlist to GDSII.
• Own project execution and technical delivery for blocks/projects.
• Lead floorplanning, power planning, placement, CTS, routing, optimization, and signoff activities.
• Drive timing closure for setup and hold across multiple modes and corners.
• Perform and review MCMM STA analysis and resolve timing issues.
• Drive PPA optimization across performance, power, and area targets.
• Analyze and resolve congestion, transition, capacitance, fanout, DRC, and routing violations.
• Drive IR Drop, EM, Signal Integrity, Crosstalk, DRC/LVS and physical signoff activities.
• Lead ECO implementation and timing optimization.
• Work with RTL, Synthesis, STA, DFT, PV, and Foundry teams to resolve issues.
• Drive block integration and full-chip implementation activities.
• Own tapeout readiness and ensure all signoff criteria are met.
• Provide technical direction and mentoring to junior engineers.

Skills

RTL-to-GDSII flow

Cadence Innovus

Tempus

Synopsys ICC2

Fusion Compiler

PrimeTime

PPA optimization

Timing closure

Education

B.E./B.Tech/M.E./M.Tech in Electronics/ECE/VLSI

Tools

Cadence Innovus

Tempus

Synopsys ICC2

Fusion Compiler

PrimeTime

Job description

Company: Siliconus Technologies Private Limited

Employment Type: Full-Time

Experience: 7+Years

Job Summary

Siliconus Technologies is looking for an experienced Lead Physical Design Engineer to lead and manage Physical Design activities across block-level and full-chip projects.

The ideal candidate should have strong hands-on expertise in the RTL-to-GDSII flow, excellent technical leadership skills, and the ability to independently drive PPA optimization, timing closure, physical signoff, project execution, and customer interactions.

Key Responsibilities

• Lead the end-to-end Physical Design flow from netlist to GDSII.
• Own project execution and technical delivery for assigned blocks/projects.
• Lead floorplanning, power planning, placement, CTS, routing, optimization, and signoff activities.
• Drive timing closure for setup and hold across multiple modes and corners.
• Perform and review MCMM STA analysis and resolve timing issues.
• Drive PPA optimization across performance, power, and area targets.
• Analyze and resolve congestion, transition, capacitance, fanout, DRC, and routing violations.
• Drive IR Drop, EM, Signal Integrity, Crosstalk, DRC/LVS and physical signoff activities.
• Lead ECO implementation and timing optimization.
• Work closely with RTL, Synthesis, STA, DFT, PV, and Foundry teams to resolve technical issues.
• Drive block integration and full-chip implementation activities.
• Own tapeout readiness and ensure all signoff criteria are met.
• Provide technical direction, mentoring, and guidance to junior and mid-level Physical Design engineers.
• Review team deliverables and ensure adherence to project methodologies and quality standards.
• Plan task allocation, track project progress, and ensure deliverables are completed within timelines.
• Identify technical risks and proactively develop solutions to avoid project delays.
• Participate in customer meetings, technical discussions, status calls, and project reviews.
• Support estimation, resource planning, and technical proposals for new projects.
• Develop and improve Physical Design methodologies and automation flows.
• Use Tcl / Perl / Python / Shell scripting for flow automation and productivity improvements.

Required Technical Skills

• Strong hands-on experience in the complete RTL-to-GDSII Physical Design flow.
  • Physical Verification
• Strong understanding of MCMM, Setup/Hold, OCV/AOCV/POCV and timing constraints.
• Good knowledge of IR Drop, EM, Signal Integrity and Crosstalk.
• Strong understanding of DRC, LVS, Antenna and other physical signoff checks.
• Strong experience with Tcl scripting; Perl/Python/Shell is an added advantage.
• Hands-on experience with Cadence Innovus / Tempus and/or Synopsys ICC2 / Fusion Compiler / PrimeTime.
• Experience with advanced technology nodes such as 28nm, 16nm, 14nm, 7nm and below is preferred.
• Strong understanding of PPA optimization and design convergence.

Leadership & Management Skills

• Ability to lead a Physical Design team and take complete technical ownership.
• Ability to distribute tasks and track team progress effectively.
• Strong problem-solving and decision-making skills.
• Ability to review and technically mentor team members.
• Strong communication and interpersonal skills.
• Ability to interact confidently with customers and cross-functional teams.
• Ability to manage multiple priorities and deliver projects within committed timelines.
• Should be capable of independently driving a project from implementation through tapeout.

Qualifications

• B.E./B.Tech/M.E./M.Tech in Electronics, Electrical, ECE, VLSI, or related engineering discipline.
• 7+years of relevant Physical Design experience.
• Proven experience leading Physical Design teams/projects.
• Strong block-level and/or full-chip implementation experience.
• Multiple tapeout experience is highly preferred.

Preferred Experience

• Experience working with global semiconductor customers.
• Experience in advanced-node SoC designs.
• Exposure to low-power implementation / UPF.
• Experience in full-chip integration and signoff.
• Strong experience in PPA optimization and timing convergence.
• Experience handling technical escalations and customer issues.
• Experience in building and improving Physical Design methodologies.

What We Offer

• Opportunity to lead advanced semiconductor and SoC projects.
• Exposure to multiple technology nodes and industry-standard EDA tools.
• Opportunity to work on end-to-end RTL-to-GDSII and tapeout projects.
• Technical and leadership growth opportunities.
• Collaborative and engineering-driven work environment.

Join Siliconus Technologies and lead the next generation of semiconductor Physical Design solutions.