Physical Design Lead

Cyient; Bengaluru; On-site; INR 1,800,000 - 2,600,000; Full time

Job summary

Cyient Semiconductors in Bengaluru is seeking an experienced Lead Physical Design Engineer to drive end-to-end physical implementation of complex ASIC/SoC designs.

You will lead floorplanning, CTS, routing, and sign-off across mature and advanced nodes, collaborating with RTL, STA, DFT, and packaging teams to ensure successful tape-outs.

This role requires 8+ years of hands-on PD experience, strong EDA tool expertise, and proven leadership abilities.

Qualifications

• 8+ years of hands-on experience in Physical Design for complex ASIC/SoC designs.
• RTL-to-GDSII physical design implementation for block-level and full-chip designs.
• Floorplanning, power planning, placement, CTS, routing, physical optimization and sign-off.
• Timing closure, IR drop, EM, congestion analysis and physical ECO implementation.
• Physical verification including LVS, DRC, ERC and antenna checks with sign-off tools.
• Tape-out experience on legacy and mature nodes with exposure to advanced nodes.
• Expertise with Cadence Innovus, Synopsys ICC2, PrimeTime, Calibre, StarRC.
• Understanding of timing constraints, sign-off methodologies, low-power design, DFM, ECOs.
• Ability to collaborate with RTL, STA, DFT, Package and cross-functional teams.
• Technical leadership: mentoring, design reviews, project planning, execution.
• Strong analytical, debugging, communication and stakeholder management.
• Available to join immediately or on short notice.

Responsibilities

• Drive end-to-end RTL-to-GDSII physical design implementation for ASIC/SoC.
• Lead floorplanning, power planning, placement, CTS, routing and optimization.
• Own timing closure, IR drop, EM, congestion analysis and sign-off.
• Oversee physical verification (LVS/DRC/ERC/antenna checks) using standard tools.
• Mentor junior engineers and conduct design reviews with cross-functional teams.
• Coordinate tape-out readiness across legacy and advanced process nodes.

Skills

Physical Design

RTL to GDSII

Floorplanning

Power Planning

Placement

Clock Tree Synthesis

CTS

Routing

Physical Optimization

Sign-off

Timing Closure

IR Drop

Electromigration

Congestion Analysis

Physical ECO Implementation

LVS

DRC

Antenna Checks

Tape-out

Legacy Nodes

Advanced Nodes

Education

B.E./B.Tech in Electronics or related

Tools

Cadence Innovus

Synopsys ICC2

PrimeTime

Calibre

StarRC

Job description

Cyient Semiconductors is looking for an experienced Lead Physical Design Engineer to drive the end‑to‑end physical implementation of complex ASIC/SoC designs.

Key Responsibilities & Required Skills:

• 8+ years of hands‑on experience in Physical Design for complex ASIC/SoC designs.
• Perform end‑to‑end RTL‑to‑GDSII physical design implementation for block‑level and full‑chip designs.
• Hands‑on expertise in floorplanning, power planning, placement, Clock Tree Synthesis (CTS), routing, physical optimization, and sign‑off.
• Strong experience in timing closure, IR drop, Electromigration (EM), congestion analysis, and physical ECO implementation.
• Hands‑on experience with physical verification, including LVS, DRC, ERC, and antenna checks, using industry‑standard sign‑off tools.
• Proven tape‑out experience on legacy and mature technology nodes (180nm, 130nm, 110nm, 90nm, 65nm, 55nm, 45nm, and 40nm), with exposure to advanced nodes such as 28nm, 16/14nm, 10nm, 7nm, 5nm, and below.
• Strong expertise with Cadence Innovus, Synopsys ICC2, PrimeTime, Calibre, StarRC, and other industry‑standard EDA tools.
• Good understanding of timing constraints, sign‑off methodologies, low‑power design techniques, DFM, hierarchical implementation flows, and physical ECOs.
• Ability to collaborate effectively with RTL, STA, DFT, Package, and other cross‑functional engineering teams to ensure successful tape‑outs.
• Provide technical leadership by mentoring junior engineers, conducting design reviews, supporting project planning, and driving successful project execution.
• Strong analytical, debugging, communication, and stakeholder management skills.
• Candidates who can join immediately or within a short notice period will be preferred.

Educational Qualification:

• B.E./B.Tech or M.E./M.Tech in Electronics, VLSI Design, or related disciplines