Senior Engineer - Physical Design

MosChip; Hyderabad; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

MosChip in Hyderabad is seeking an experienced ASIC Physical Design engineer to drive block level floorplanning, P&R, timing closure and SI/DRC/LVS checks on advanced nodes.

You will mentor PD engineers, interface with front-end teams, and apply Cadence, Synopsys or Magma tools, with scripting in Perl/TCL.

Qualifications

• Experience with 45nm/28nm or lower nodes and low-power techniques.
• Strong ASIC PD background: floorplanning, P&R, extraction, IR drop, timing and SI closure.
• Proficient with Cadence/Synopsys/Magma tools and scripting in Perl/TCL.

Responsibilities

• Block level and top-level floor planning, PG planning and partitioning.
• Placement, scan-chain reordering, clock tree synthesis and timing optimization.
• SI aware routing, DRC/LVS/antenna checks and ECOs (timing/functional).
• Interface with front-end ASIC teams to resolve issues.
• Mentor and guide PD engineers; ensure clear documentation and plans.
• Static Timing Analysis in PrimeTime or PrimeTime-SI.

Skills

Perl scripting

TCL scripting

Physical verification

Tools

Cadence

Synopsys

Magma

Job description

Responsibilities

• Block level / top-level floor planning, PG Planning, partitioning (for hierarchical designs), placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks and be able to fix the violations.


• Should have worked on 45nm, 28nm or lower node designs with advanced low power techniques such as Voltage Islands, Power Gating and substrate-bias.


• Provide technical guidance, mentoring to physical design engineers.


• Interface with front-end ASIC teams to resolve issues.


• Excellent communication skills.


• Strong background of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure.


• Extensive experience and detailed knowledge in Cadence or Synopsys or Magma physical Design Tools.


• Expertise in scripting languages such as PERL, TCL.


• Strong Physical Verification skill set.


• Static Timing Analysis in Primetime or Primetime-SI.


• Good written and oral communication skills. Ability to clearly document plans.


• Ability to interface with different teams and prioritize work based on project needs.

Experience

• Experience 3 to 8 Years

Location

• Hyderabad