Staff Physical Design Engineer

LeadSoc Technologies Pvt Ltd; Bengaluru; On-site; INR 3,500,000 - 5,500,000; Full time

Job summary

LeadSoc Technologies Pvt Ltd in Bengaluru is seeking a Staff Physical Design Engineer with hands-on expertise in full-chip physical implementation, timing closure, and signoff for complex SoCs.

You will own RTL-to-GDSII implementation, drive MCMM/STA closure, ECOs and critical path optimization, and collaborate with RTL, STA, DFT and PD teams to ensure tapeout readiness. Proficiency with Synopsys ICC2, PrimeTime and scripting (Tcl/Python) is highly valued.

Qualifications

• Strong full-chip Physical Design / ASIC implementation experience.
• Hands-on with ICC2, Fusion Compiler, PrimeTime or equivalent.
• Deep understanding of STA, MCMM, CTS, timing closure and ECO methodology.
• Expertise in floorplanning, power planning, placement and routing.
• Experience with advanced-node SoCs and complex clocking architectures preferred.
• Strong scripting and debugging skills.

Responsibilities

• Own full-chip RTL-to-GDSII implementation across synthesis, floorplanning, placement, CTS, routing and signoff.
• Drive MCMM STA, setup/hold closure, ECOs and critical path optimization.
• Resolve congestion, IR/EM, signal integrity, DRC/LVS and PD issues.
• Optimize PPA, timing, power and area across implementation stages.
• Collaborate with RTL, STA, DFT, PD and signoff teams to drive tapeout readiness.
• Develop and enhance PD flows and automation using Tcl/Python/Perl.

Skills

Full-chip PD

Scripting Tcl/Python

ICC2/PrimeTime

Floorplanning & Routing

Timing Closure

Tools

Synopsys ICC2

PrimeTime

Design Compiler

Job description

We are looking for a Staff Physical Design Engineer with strong hands-on expertise in full-chip physical implementation, timing closure, and signoff for complex SoC designs.

Key Responsibilities

• Own full-chip RTL-to-GDSII implementation across synthesis, floorplanning, placement, CTS, routing and signoff.
• Drive MCMM STA, setup/hold closure, ECOs and critical path optimization.
• Resolve congestion, IR/EM, signal integrity, DRC/LVS and physical design issues.
• Optimize PPA, timing, power and area across implementation stages.
• Collaborate with RTL, STA, DFT, PD and signoff teams to drive tapeout readiness.
• Develop and enhance PD flows and automation using Tcl/Python/Perl.

Core Technical Skills

• Strong full-chip Physical Design / ASIC implementation experience.
• Hands-on with Synopsys ICC2/Fusion Compiler, PrimeTime, Design Compiler or equivalent.
• Deep understanding of STA, MCMM, CTS, timing closure and ECO methodology.
• Strong expertise in floorplanning, power planning, placement and routing.
• Experience with advanced-node SoCs and complex clocking architectures preferred.
• Strong scripting and debugging skills.

Ideal Candidate:

A highly hands-on Physical Design engineer who can independently drive full-chip implementation and timing closure through tapeout.