Physical Design Lead – Place & Route (PnR) / Static Timing Analysis (STA)

Best NanoTech; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Best NanoTech in Bengaluru is seeking a Physical Design Lead to drive end-to-end ASIC/SoC implementation, overseeing Place & Route, CTS, STA, and signoff. The role collaborates with RTL, DFT, design verification, and packaging teams to ensure robust silicon.

The ideal candidate has 8–15 years in physical design across advanced nodes, with a proven tape-out track record and strong leadership to mentor teams and optimize PPA while meeting project schedules.

Qualifications

• Bachelor's or Master's degree in Electronics, Electrical, or Computer Engineering.
• 8–15 years of hands-on ASIC/SoC physical design experience.
• Proven tape-out leadership in advanced technology nodes.
• Strong understanding of the complete semiconductor implementation flow.

Responsibilities

• Lead ASIC/SoC physical design from netlist to GDSII signoff.
• Drive floorplanning, power planning, placement, CTS, routing, optimization & verification.
• Perform timing closure across multiple PVT corners.
• Mentor junior engineers and coordinate with RTL/DFT/Packaging teams.
• Develop design methodologies and automation flows.

Skills

PnR

CTS

STA

Physical Design

Mentoring

Education

Bachelors/Masters in Electronics/EE/CE

Tools

GDSII

EDA tools

STA tools

Job description

Physical Design Lead Place & Route (PnR) / Static Timing Analysis (STA)

Work Mode: Onsite

Experience: 8 -15 Years

Role Overview

We are seeking an experienced Physical Design Lead to drive the complete physical implementation flow for complex ASIC and SoC designs targeting advanced semiconductor technologies. The role involves leading Place & Route (PnR), Clock Tree Synthesis (CTS), Static Timing Analysis (STA), Physical Verification, Power Optimization, and Signoff while collaborating closely with RTL, DFT, Design Verification, Package, and Product Engineering teams.

The ideal candidate will have extensive experience delivering multiple successful tape-outs across advanced process nodes and possess strong leadership capabilities to mentor engineering teams and drive high-quality silicon implementation.

Key Responsibilities

• Lead complete ASIC/SoC physical design implementation from netlist through GDSII signoff.
• Drive floorplanning, power planning, placement, clock tree synthesis (CTS), routing, optimization, and physical verification activities.
• Perform timing closure across multiple process, voltage, and temperature (PVT) corners.
• Optimize designs for Power, Performance, and Area (PPA) while meeting schedule and quality objectives.
• Conduct Static Timing Analysis (STA) and resolve setup, hold, clock skew, and signal integrity issues.
• Perform physical verification including DRC, LVS, ERC, antenna, and electromigration (EM/IR) analysis.
• Collaborate with RTL, DFT, Design Verification, Package Design, and Process Technology teams throughout the design cycle.
• Lead engineering reviews, design signoff, ECO implementation, and tape-out readiness activities.
• Develop and enhance physical design methodologies, automation flows, and reusable scripts.
• Mentor junior engineers and provide technical leadership across multiple projects.
• Support silicon bring-up and post-silicon debug where required.
• Coordinate with global engineering teams to ensure successful execution of complex semiconductor programs.

Required Qualifications

• Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or related discipline.
• 8 15 years of hands-on experience in ASIC or SoC Physical Design.
• Proven experience leading successful tape-outs in advanced technology nodes.
• Strong understanding of the complete semiconductor implementation flow.