Senior Physical Design Engineer/Lead

Neurealm; Bengaluru; On-site; INR 1,500,000 - 2,100,000; Full time

Job summary

Neurealm in Bengaluru is seeking an experienced ASIC/FPGA design engineer to own the full PnR flow for block and top-level designs. You will drive floor-planning, placement, CTS, power routing and timing closure on complex chips.

Ideal candidates have hands-on experience with 14nm or smaller nodes, STA and physical verification (DRC/LVS), and use Innovus for implementation and signoff fixes, with strong power and timing optimization knowledge.

Qualifications

• 4 to 15 years experience in relevant field.
• Experience in Full PnR flow including Floor-planning, Placement, CTS, Power Routing, Timing Closure.
• Hands-on experience with 14nm or smaller nodes.
• Expertise in STA and Physical Verification (DRC/LVS).
• Hands-on experience with Innovus tool.
• Experience with Signoff fixes.
• Knowledge of power and timing optimization techniques.

Responsibilities

• Lead Full PnR flow for block and top-level designs.
• Apply advanced node technologies (14nm) in design flows.
• Perform STA and Physical Verification (DRC/LVS) activities.
• Utilize Innovus for implementation and signoff fixes.
• Optimize power and timing performances of the design.

Skills

Full PnR flow

Floor-planning

Placement

CTS

Power Routing

Timing Closure

STA

Physical Verification

DRC/LVS

Innovus

Signoff fixes

Power optimization

Timing optimization

Tools

Innovus

Job description

Experience: 4 to 15 years

Immediate joiners preferred

Job Description

• In-depth experience in Full PnR flow (Floor-planning, Placement, CTS, Power Routing, and Timing Closure) for block and top-level designs.
• Hands‑on experience with advanced technology nodes (14nm or lesser).< /li>
• Strong expertise in STA and Physical Verification (DRC/LVS).
• Must have hands‑on experience with the Innovus tool.
• Hands‑on experience with Signoff fixes.
• Knowledge in power optimization and timing optimization techniques.