Senior Staff Physical Design Engineer

MaxLinear, Inc.; Bengaluru; On-site; INR 1,200,000 - 1,600,000; Full time

Job summary

MaxLinear, Inc. is seeking an experienced Sr. Staff Physical Design Engineer in Bengaluru, India. This role involves leading end-to-end physical design for complex SoCs and large digital blocks, ensuring timing closure, power integrity, and sign-off.

The ideal candidate has over 7 years of experience in ASIC design, a strong grasp of Cadence tools, and excellent communication skills. Collaboration with cross-functional teams is essential. This position also emphasizes mentorship and quality assurance.

Qualifications

• 7+ years of experience in ASIC physical design.
• Proven track record of successful ASIC tape-outs.
• Strong hands-on experience with Cadence tools.

Responsibilities

• Lead end-to-end physical design for complex SoCs and large blocks.
• Drive static timing analysis, power integrity analysis, and DRC/LVS sign-off.
• Develop and enhance P&R flow automation.

Skills

ASIC physical design

Cadence Innovus

Cadence Tempus

Cadence Voltus

Calibre DRC/LVS

Linux/Unix scripting

Education

Bachelor’s or Master’s in Electrical / Electronics Engineering

Tools

Tcl

Python

Perl

Shell scripting

Job description

Responsibilities

We are seeking an experienced Sr. Staff Physical Design Engineer to lead end‑to‑end physical design for complex SoCs and large digital blocks. The role involves ownership of floorplanning, placement, CTS, routing, timing closure, and physical sign‑off across MMMC scenarios.

You will drive STA, IR/EM, power integrity, and DRC/LVS sign‑off, support ECOs, and enhance P&R methodologies through automation. Close collaboration with RTL, STA, DFT, and verification teams is key, along with mentoring junior engineers. You will focus on:

Physical Design & Implementation

• Own end‑to‑end place‑and‑route execution for complex SoCs and large digital blocks
• Perform floorplanning, placement, clock tree synthesis (CTS), routing, and optimization
• Drive timing closure across multi‑mode, multi‑corner (MMMC) scenarios
• Solve challenging setup/hold, clocking, and CDC‑related timing issues

Sign‑off & Quality Closure

• Perform static timing analysis (STA) and constraint debugging at block and full‑chip level
• Lead IR drop, EM, and power integrity analysis, and implement corrective actions
• Execute and debug physical verification (DRC/LVS) to achieve clean sign‑off
• Support ECO flows, late‑stage fixes, and post‑layout optimization

Methodology & Automation

• Develop, enhance, and maintain P&R flow automation using Tcl, Python, Perl, and shell scripting
• Improve turnaround time, QoR, and repeatability through methodology enhancements
• Review and contribute to physical design guidelines and best practices

Cross‑Functional Collaboration

• Work closely with RTL design, STA, verification, DFT, and architecture teams
• Provide early physical feasibility feedback on clocking, floorplan, and RTL structures
• Mentor junior engineers and act as a technical point of reference within the PD team

Qualifications

• Bachelor’s degree or Master’s in Electrical / Electronics Engineering or related field
• 7+ years of experience in ASIC physical design
• Proven track record of successful ASIC tape‑outs at block or full‑chip level
• Strong hands‑on experience with:
  • Place & Route: Cadence Innovus
  • STA: Cadence Tempus
  • IR/EM: Cadence Voltus, RedHawk
  • Physical Verification: Calibre DRC/LVS
• Solid understanding of:
  • Clock tree architectures and skew management
  • Timing constraints (false paths, multicycle paths, generated clocks)
  • Power‑aware design techniques and low‑power sign‑off
• Proficiency in Linux/Unix environments and scripting for flow automation

Soft Skills & Attributes

• Strong analytical and debugging skills
• Ability to work independently with minimal supervision
• Clear communication skills for cross‑site and cross‑functional collaboration
• Quality‑driven mindset with strong ownership and accountability

Nice to Have

• Experience with mixed‑signal SoCs or power‑management related designs
• Familiarity with advanced clocking schemes and low‑frequency / high‑variation clocks
• Experience supporting post‑silicon debug or gate‑level simulation (GLS)