Physical Design-Full Chip Lead

HCLTech; Bengaluru; On-site; INR 3,500,000 - 5,200,000; Full time

Job summary

HCL Technologies Limited is hiring a Physical Design Lead to spearhead full-chip PD lifecycle for high-performance SoCs. The role requires ownership of floorplanning, PnR, CTS, and sign-off across STA, EMIR, and PDN definitions.

You will mentor junior engineers and partner with architects and foundries to achieve best-in-class PPA on advanced nodes. The ideal candidate has 15+ years of hands-on PD experience, strong leadership, and deep scripting ability.

Qualifications

• 15+ years in physical design of complex SoCs.
• Experience leading full-chip tape-outs and tight PPA targets.
• Expertise in floorplanning, synthesis, CTS, PnR, DRC/LVS/EMIR.

Responsibilities

• Lead the full-chip physical design lifecycle from RTL to GDSII tape-out.
• Define sign-off criteria for STA, EMIR, UPF, DRC/LVS/ERC.
• Drive top-level floorplanning, PDN, and macro integration.
• Coordinate with RTL, DV, DFT, Packaging, and foundries for sign-off.
• Mentor engineers and drive technical reviews within the PD team.

Skills

Full-chip tape-outs

SoC flow mastery

Scripting (TCL/Python/Shell)

Clock-tree architectures

Low-power design (UPF)

Tools

Synopsys Fusion Compiler

Synopsys IC Compiler II

Synopsys PrimeTime

Synopsys StarRC

Synopsys VC LP

Cadence Innovus

Cadence Tempus

Cadence Quantus

Cadence Pegasus

Cadence Voltus

Job description

We are Hiring: Physical Design Lead - Full Chip

Years of Experience: Min 15+ Years

Job Summary:

We are seeking a highly technical and execution-driven Physical Design Chip Lead to spearhead the structural design, implementation, and physical sign-off of our next-generation, high-performance SoCs. In this role, you will own the entire full-chip physical design lifecycle—from early architectural feasibility, floorplanning, and synthesis through final GDSII tape-out. You will lead a team of talented physical design engineers, establish sign-off methodologies, and collaborate directly with architects, front-end designers, and foundry partners to deliver best-in-class Power, Performance, and Area (PPA) on advanced process nodes. Key responsibilities:

• Drive the execution of the entire hierarchical RTL-to-GDSII physical design flow, including synthesis, floorplanning, place & route (PnR), clock tree synthesis (CTS), timing closure, and physical verification.
• Define the physical implementation strategy, schedule milestones, and allocate resources across block-level and full-chip integration tasks. Identify and mitigate technical or schedule risks early.
• Partner with SoC architects to conduct early feasibility studies. Drive top-level floorplanning, package/bump placement, macro integration, and full-chip Power Distribution Network (PDN) definitions.
• Establish strict sign-off criteria and methodologies for the project across all domains: Static Timing Analysis (STA), Electromigration and IR Drop (EMIR), Low Power Compliance (VCLP/UPF), and Physical Verification (DRC/LVS/ERC).
• Act as the primary engineering bridge between RTL Front-End, Design Verification (DV), DFT, Packaging, Signal/Power Integrity, and external Silicon Foundries.
• Lead the final closure push for the full-chip database, auditing waivers, reviewing engineering change orders (ECOs), and authorizing final tape-out release.
• Guide, mentor, and perform technical reviews for junior and mid-level physical design engineers to elevate the team's technical capabilities

Technical Skills:

• With a proven track record of leading or co-leading complex full-chip SoC tape-outs.
• Core flow mastery: Synopsys (Fusion Compiler, IC Compiler II, PrimeTime, StarRC, VC LP) or Cadence (Innovus, Tempus, Quantus, Pegasus, Voltus).
• Advanced nodes: Extensive tape-out experience on sub-7nm FinFET or GAA process nodes (e.g., TSMC/Intel/Samsung N5, N3, N2) handling tight design rules and complex multi-patterning layouts.
• Advanced clock-tree architectures, hierarchical UPF low-power designs, and chip-package co-design.
• Proficient in TCL/python/Shell.