Physical Design Lead

Best NanoTech; Bengaluru; On-site; INR 4,500,000 - 7,500,000; Full time

Job summary

Best NanoTech is seeking an experienced Physical Design Lead for Bengaluru to drive end-to-end ASIC PD from floorplanning to GDSII signoff. You will optimize CTS, routing, timing, and signoff across advanced nodes such as 7nm/5nm/3nm.

You will mentor PD engineers, coordinate cross-functional teams, and develop automation to improve throughput and reliability. Strong leadership and tapeout experience are essential.

Qualifications

• 7–10 years of hands-on ASIC Physical Design experience.
• Experience with 7nm/5nm/3nm nodes and tapeouts.
• 1–2 years of team handling or technical leadership experience.

Responsibilities

• Lead end-to-end ASIC Physical Design implementation from floorplanning to GDSII signoff.
• Perform floorplanning, power planning, placement, CTS, routing, and optimization.
• Drive Physical Design implementation at advanced technology nodes, preferably 7nm, 5nm, or 3nm.
• Execute Static Timing Analysis (STA), timing optimization, and timing closure across multiple corners and modes.
• Perform setup and hold timing analysis, constraint validation, and timing signoff.
• Manage physical verification activities, including DRC, LVS, and physical signoff.
• Develop and maintain TCL, Python, Perl, and Make-based automation scripts.
• Lead and mentor Physical Design engineers, review implementation quality, and coordinate technical deliverables.
• Collaborate with RTL Design, DFT, STA, and Physical Verification teams to resolve implementation and signoff issues.

Skills

RTL to GDSII

Floorplanning

CTS

STA

Physical verification

Python scripting

Leadership

Education

Bachelors/Masters in ECE/VLSI

Tools

TCL

Python

Perl

Make

Job description

We are looking for an experienced Physical Design Lead with 7–10 years of hands-on experience in ASIC Physical Design and implementation. The candidate should have strong expertise in end-to-end RTL-to-GDSII implementation, advanced technology nodes (7nm/5nm/3nm), timing closure, physical verification, and signoff. The role requires full-chip implementation and successful tapeout experience, along with 1–2 years of technical team leadership.

2. Key Responsibilities

• Lead end-to-end ASIC Physical Design implementation from floorplanning to GDSII signoff.
• Perform floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and optimization.
• Drive Physical Design implementation at advanced technology nodes, preferably 7nm, 5nm, or 3nm.
• Execute Static Timing Analysis (STA), timing optimization, and timing closure across multiple corners and modes.
• Perform setup and hold timing analysis, constraint validation, and timing signoff.
• Manage physical verification activities, including DRC, LVS, and physical signoff.
• Perform power integrity analysis, including IR Drop and Electromigration (EM) checks.
• Work on full-chip and block-level Physical Design implementation.
• Support design integration, signoff closure, and successful ASIC tapeouts.
• Develop and maintain TCL, Python, Perl, and Make-based automation scripts.
• Lead and mentor Physical Design engineers, review implementation quality, and coordinate technical deliverables.
• Collaborate with RTL Design, DFT, STA, and Physical Verification teams to resolve implementation and signoff issues.

3. Required Qualifications

• Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, Microelectronics, or a related discipline.
• 7–10 years of hands-on experience in ASIC Physical Design.
• 1–2 years of team handling or technical leadership experience.
• Strong understanding of semiconductor design methodologies and RTL-to-GDSII implementation.
• Hands-on experience with advanced technology nodes, preferably 7nm/5nm/3nm.
• Demonstrated experience in full-chip implementation and successful tapeouts.
• Strong understanding of Physical Design signoff requirements and timing closure.