Staff Physical Design Engineer

Sykatiya Technologies Pvt Ltd; Bengaluru; Hybrid; INR 4,000,000 - 7,000,000; Full time

Job summary

Sykatiya Technologies Pvt Ltd in Bengaluru is seeking a Techno-Functional Lead / Staff Physical Design Engineer with 10+ years of hands-on experience to drive complex ASIC/SoC physical design in a hybrid environment.

You will serve as the technical authority for physical implementation, guiding floorplanning, power integrity, timing, and verification while coordinating with architecture, DFT, and foundry partners to ensure on-time tape-outs with optimal PPA.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics & Communication Engineering, Microelectronics, or a related field.
• 10+ years of hands-on physical design experience with tape-outs on advanced nodes (7nm and below).
• Proficiency in standard EDA tool suites (Synopsys, Cadence).
• Advanced scripting in Tcl, Python, or Perl for automation and workflows.

Responsibilities

• RTL-to-GDSII execution: floorplanning, power grid design, placement, CTS, routing, SI, STA, and physical verification.
• Architecture & Methodology: define physical implementation methodologies and automation scripts (Tcl/Python).
• Advanced Technology Nodes: drive design closure on sub-7nm nodes (5nm, 3nm, 2nm) with UPF/CPF and thermal management.
• Cross-Functional Collaboration: partner with Architecture, DFT, Physical Verification, and Synthesis teams to resolve timing, floorplan, and routability bottlenecks.
• Technical Ownership & Project Planning: own sub-systems or full-chip SoC designs, define schedules, milestones, and tape-out roadmaps.
• Team Leadership & Mentorship: lead and mentor a team of physical design engineers and conduct design reviews.
• Risk & Issue Management: identify bottlenecks, formulate mitigations, and drive decisions under pressure.
• Stakeholder & Vendor Alignment: interface with foundry partners and EDA vendors to evaluate tools and licensing.

Skills

Physical design expertise

EDA tooling knowledge

Scripting (Tcl/Python/Perl)

Leadership

Education

Bachelor’s or Master’s degree in Electrical Engineering or related

Tools

Synopsys

Cadence

Job description

We are looking for a high-performing Techno-Functional Lead / Staff Physical Design Engineer with 10+ years of experience in leading complex, multi-million gate ASIC/SoC physical design projects. In this hybrid role, you will act as a primary technical authority on physical implementation while simultaneously steering execution strategy, resource allocation, risk mitigation, and stakeholder engagement. You will bridge the gap between technical execution and business delivery, ensuring complex chips tape out on time with optimal Power, Performance, and Area (PPA).

Responsibilities

Technical Leadership

• RTL-to-GDSII Execution: Direct and participate in the full physical design flow including floorplanning, power grid design, placement, CTS (Clock Tree Synthesis), routing, signal integrity (IR drop / EM), STA (Static Timing Analysis), and physical verification (DRC/LVS).
• Architecture & Methodology: Define physical implementation methodologies and custom automation scripts (Tcl/Python) tailored for ultra-low power and high-speed design constraints.
• Advanced Technology Nodes: Drive design closure on sub-7nm process nodes (e.g., 5nm, 3nm, 2nm) dealing with multi-patterning, high-density cell placement, complex power domain management (UPF/CPF), and thermal considerations.
• Cross-Functional Collaboration: Partner with Architecture, DFT, Physical Verification, and Synthesis teams to resolve complex timing, floorplan, and routability bottlenecks early in the execution cycle.

Functional & Project Management

• Technical Ownership & Project Planning: Serve as the technical owner for complex sub-systems or full-chip SoC designs; define schedules, key execution milestones, tape-out roadmaps, and delivery metrics.
• Team Leadership & Mentorship: Lead, guide, and mentor a team of physical design engineers. Conduct technical design reviews and establish standard operational procedures.
• Risk & Issue Management: Proactively identify technical, tool, or resource bottlenecks, formulate mitigation strategies, and drive decision-making processes under high pressure.
• Stakeholder & Vendor Alignment: Interface with key internal/external stakeholders, foundry partners, and EDA vendors (Synopsys, Cadence) to evaluate tools, manage software licensing needs, and resolve design enablement issues.

Required Qualifications

• Education: Bachelor’s or Master’s degree in Electrical Engineering, Electronics & Communication Engineering, Microelectronics, or a related field.
• Experience: 10+ years of hands-on physical design experience with a proven track record of successful tape-outs on advanced technology nodes (7nm and below).
• EDA Tool Proficiency: Advanced proficiency in standard EDA tool suites:
• Scripting: Advanced skills in Tcl, Python, or Perl for automated flow development and productivity enhancements.