Physical Design Lead

Mirafra Technologies; Bengaluru; On-site; INR 5,000,000 - 9,000,000; Full time

Job summary

Mirafra Technologies is seeking an experienced Physical Design / SoC Full-Chip Technical Lead to drive execution of complex next‑generation SoC designs, spanning 7nm, 5nm, 3nm and beyond, from RTL/Netlist to GDSII and tape-out.

You will lead end‑to‑end physical implementation, mentor the PD team, and collaborate with architecture, RTL, DFT, STA, power, SI, and verification to resolve challenges and deliver successful tape-outs.

Qualifications

• Strong experience in full-chip Physical Design / Physical Implementation of complex SoCs.
• Proven experience on advanced process nodes such as 7nm, 5nm, 3nm, or below.
• Thorough understanding of RTL-to-GDSII flow and end-to-end PD lifecycle.
• Hands-on expertise in Floorplanning, Synthesis, Placement, CTS, Routing, STA, SI, DRC/LVS, and EM/IR.

Responsibilities

• Lead end-to-end physical implementation of complex SoCs and large sub-systems from RTL/Netlist through GDSII and tape-out.
• Provide technical leadership and mentorship to the Physical Design team.
• Drive execution, schedules, methodologies, and deliverables across the full-chip flow.

Skills

Full-Chip PD

RTL-to-GDSII flow

Floorplanning

Synthesis

Placement

CTS

Routing

STA

SI

DRC/LVS

EM/IR

7nm

5nm

3nm

Job description

We are looking for an experienced Physical Design / SoC Full-Chip Technical Lead to drive the execution, methodology, and physical closure of complex next-generation SoC designs across advanced technology nodes, including 7nm, 5nm, 3nm, and beyond.

This role offers the opportunity to lead technically challenging full-chip implementations, collaborate closely with architecture and design teams, and own the physical implementation journey from RTL/Netlist to GDSII and tape-out.

Technical Leadership & Full-Chip Ownership

• Lead end-to-end physical implementation of complex SoCs and large sub-systems from RTL/Netlist through GDSII and tape-out.
• Provide technical leadership and mentorship to the Physical Design team.
• Drive execution, schedules, methodologies, and technical deliverables across the full-chip implementation flow.
• Partner with Architecture, RTL, DFT, STA, Power, Signal Integrity, Packaging, and Verification teams to resolve complex design challenges.

What We’re Looking For

• Strong experience in full-chip Physical Design / Physical Implementation of complex SoCs.
• Proven experience working on advanced process nodes such as 7nm, 5nm, 3nm, or below.
• Strong understanding of the complete RTL-to-GDSII flow.
• Hands-on expertise in Floorplanning, Synthesis, Placement, CTS, Routing, STA, SI, DRC/LVS, and EM/IR.
• Experience with hierarchical designs, large SoCs, complex power domains, and challenging timing closure.
• Strong problem-solving and technical leadership skills.
• Ability to work effectively across multiple engineering disciplines and drive issues to closure.
• Experience mentoring engineers and leading technical execution across complex projects.

Why Join Us?

• Work on next-generation SoCs using advanced semiconductor process technologies.
• Solve challenging problems across physical implementation, timing, power, and signal integrity.
• Work with highly experienced cross-functional engineering teams.
• Opportunity to influence physical design methodologies, automation, and execution strategy.
• Play a key role in delivering complex designs from concept to successful tape-out.