Physical Design Manager

Best NanoTech; Bengaluru; On-site; INR 4,500,000 - 7,000,000; Full time

Job summary

Best NanoTech is seeking an experienced Physical Design Manager in Bengaluru, India. You will lead PD teams across ASIC/SoC implementation and tapeout, guiding floorplanning, CTS, routing, and optimization for advanced nodes.

You will mentor engineers and collaborate with RTL, DFT, and CAD/EDA teams to ensure high-quality silicon. The role requires 12–20 years in PD with at least 3 years of people management, strong expertise in STA, physical verification, power integrity, and modern low-power

Qualifications

• Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, Microelectronics, or related discipline.
• 12-20 years of professional experience in ASIC/SoC Physical Design.
• Minimum 3 years of direct people management experience (Mandatory).
• Proven experience in leading and building Physical Design engineering teams.
• Strong hands-on experience in advanced technology node implementation.
• Demonstrated experience in full-chip Physical Design and successful tapeouts.
• Strong understanding of Physical Design methodologies, timing closure, power integrity, and physical.
• Experience using Synopsys and/or Cadence EDA tool suites.
• Ability to manage multiple technical deliverables, engineering resources, and project schedules.

Responsibilities

• Lead and manage Physical Design teams responsible for ASIC/SoC implementation and tapeout delivery.
• Drive end-to-end Physical Design activities, including Floorplanning, Placement, CTS, Routing, and Physical optimization.
• Manage full-chip and block-level Physical Design implementation across advanced technology nodes.
• Provide leadership for STA, timing closure, and signal integrity.
• Oversee Power Integrity analysis, including EM, IR drop, and PDN optimization.
• Ensure Physical Verification and compliance (DRC, LVS, etc.).
• Lead low-power implementation using UPF/CPF and multi-voltage design.
• Drive PPA optimization across the PD flow.
• Manage project planning, resources, schedules, risks, and tapeout milestones.
• Develop PD teams through reviews, performance management, and capability development.
• Collaborate with RTL, DFT, STA, Verification, CAD/EDA, and SoC teams to resolve issues.
• Establish PD methodologies and ensure successful silicon tapeout.

Skills

Physical Design

STA

Physical Verification

Power Integrity

Team Leadership

Education

Bachelor's/Master's in Electronics/VLSI

Tools

Synopsys EDA

Cadence EDA

Job description

We are looking for an experienced Physical Design Manager with 12-20 years of expertise in ASIC/SoC Physical Design and a minimum of 3 years of people management experience.

The role involves leading Physical Design teams, managing end-to-end chip implementation, and ensuring successful tapeouts across advanced semiconductor technology nodes.

The candidate should possess strong technical expertise in Physical Design, STA, Physical Verification, Power Integrity, and along with proven team-building and project delivery experience.

3. Key Responsibilities

• Lead and manage Physical Design engineering teams responsible for ASIC/SoC implementation and tapeout delivery.
• Drive end-to-end Physical Design activities, including Floorplanning, Placement, Clock Tree Synthesis (CTS), Routing, Optimization, and Physical
• Manage full-chip and block-level Physical Design implementation across advanced technology nodes.
• Provide technical leadership for Static Timing Analysis (STA), Timing Closure, and Signal Integrity (SI).
• Oversee Power Integrity analysis, including Electromigration (EM), IR Drop, and Power Delivery Network (PDN) optimization.
• Ensure Physical Verification and compliance, including DRC, LVS, and related checks.
• Lead low-power implementation methodologies using UPF/CPF and multi-voltage design techniques.
• Drive PPA (Power, Performance, Area) optimization throughout the Physical Design flow.
• Manage project planning, resource allocation, engineering schedules, technical risks, and tapeout milestones.
• Build, mentor, and develop Physical Design teams through technical reviews, performance management, and capability development.
• Collaborate with RTL Design, DFT, STA, Verification, CAD/EDA, and SoC Integration teams to resolve implementation challenges.
• Establish Physical Design methodologies, review design quality, and ensure successful silicon tapeout execution.

4. Required Qualifications

• Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, Microelectronics, or a related discipline.
• 12-20 years of professional experience in ASIC/SoC Physical Design.
• Minimum 3 years of direct people management experience (Mandatory).
• Proven experience in leading and building Physical Design engineering teams.
• Strong hands-on experience in advanced technology node implementation.
• Demonstrated experience in full-chip Physical Design and successful tapeouts.
• Strong understanding of Physical Design methodologies, timing closure, power integrity, and physical.
• Experience using Synopsys and/or Cadence EDA tool suites.
• Ability to manage multiple technical deliverables, engineering resources, and project schedules.