SOC Full-Chip Physical Design Engineer

Mirafra Technologies; Bengaluru Urban; On-site; INR 3,500,000 - 6,000,000; Full time

Job summary

Mirafra Technologies in Bengaluru seeks an experienced Physical Design / SoC Full-Chip Technical Lead to drive execution, methodology, and physical closure of advanced SoCs on 7nm, 5nm, 3nm and beyond. Lead full-chip implementations from RTL/Netlist to GDSII and tape-out, collaborating with architecture and design teams.

You will provide technical leadership, mentor the PD team, define schedules and flows, and coordinate with RTL, DFT, STA, Power, SI, and verification groups to deliver on-time

Qualifications

• Experience in full-chip physical design of complex SoCs (RTL-to-GDSII).
• Hands-on expertise across floorplanning, placement, routing, CTS, STA, DRC/LVS, EM/IR.
• Proven leadership and mentoring of Physical Design teams.
• Experience on advanced process nodes (7nm/5nm/3nm or below).

Responsibilities

• Lead end-to-end physical implementation of complex SoCs from RTL/Netlist to GDSII and tape-out.
• Provide technical leadership and mentorship to the Physical Design team.
• Drive execution, schedules, methodologies, and deliverables across the full-chip flow.
• Collaborate with Architecture, RTL, DFT, STA, Power, SI, Packaging and Verification teams to resolve design challenges.

Skills

Full-chip PD

RTL-to-GDSII flow

Floorplanning

Placement & Routing

STA

Power integrity

Signal Integrity

DRC/LVS

Mentorship

Timing closure

Job description

Role: We are looking for an experienced Physical Design / SoC Full-Chip Technical Lead to drive the execution, methodology, and physical closure of complex next-generation SoC designs across advanced technology nodes, including 7nm, 5nm, 3nm, and beyond.

This role offers the opportunity to lead technically challenging full-chip implementations, collaborate closely with architecture and design teams, and own the physical implementation journey from RTL/Netlist to GDSII and tape-out.

Technical Leadership & Full-Chip Ownership

• Lead end-to-end physical implementation of complex SoCs and large sub-systems from RTL/Netlist through GDSII and tape-out.
• Provide technical leadership and mentorship to the Physical Design team.
• Drive execution, schedules, methodologies, and technical deliverables across the full-chip implementation flow.
• Partner with Architecture, RTL, DFT, STA, Power, Signal Integrity, Packaging, and Verification teams to resolve complex design challenges.

What We're Looking For

• Strong experience in full-chip Physical Design / Physical Implementation of complex SoCs.
• Proven experience working on advanced process nodes such as 7nm, 5nm, 3nm, or below.
• Strong understanding of the complete RTL-to-GDSII flow.
• Hands-on expertise in Floorplanning, Synthesis, Placement, CTS, Routing, STA, SI, DRC/LVS, and EM/IR.
• Experience with hierarchical designs, large SoCs, complex power domains, and challenging timing closure.
• Strong problem-solving and technical leadership skills.
• Ability to work effectively across multiple engineering disciplines and drive issues to closure.
• Experience mentoring engineers and leading technical execution across complex projects.

Why Join Us?

• Work on next-generation SoCs using advanced semiconductor process technologies.
• Solve challenging problems across physical implementation, timing, power, and signal integrity.
• Work with highly experienced cross-functional engineering teams.
• Opportunity to influence physical design methodologies, automation, and execution strategy.
• Play a key role in delivering complex designs from concept to successful tape-out.