Physical Design Engineer

Broadcom Inc.; Pune District; On-site; INR 3,000,000 - 7,000,000; Full time

Job summary

Broadcom Inc. is seeking an experienced STA Engineer to lead timing closure for block and full-chip designs.

You will apply Broadcom's design methodology to ensure robust timing closure and signoff readiness across modes and corners. This role requires detailed setup/hold analysis, constraint development, and ECO-driven optimizations through tape-out.

Qualifications

• MSEE/MSCS with 10+ years of experience in Static Timing Analysis and timing closure for block/full-chip designs.
• Strong understanding of CMOS fundamentals, timing concepts and semiconductor design flow.
• Hands-on experience in setup/hold analysis, path-based analysis, derates, and MMMC concepts.

Responsibilities

• Perform full-chip and block-level STA across all modes and corners.
• Analyze and debug setup/hold/clock-gating timing violations.
• Develop and maintain timing constraints including SDC creation and signoff readiness.
• Drive timing closure through ECO implementation and timing optimization.
• Analyze timing impact due to process, voltage, and temperature variations.
• Support timing signoff for pre-layout and post-layout stages.
• Generate timing reports and communicate closure status to stakeholders.

Skills

Static Timing Analysis

Timing Closure

SDC/Constraints

Clock tree & jitter

Scripting (Tcl/Python/Perl)

Education

MSEE/MSCS

BSEE/BSCS

Tools

Synopsys PrimeTime

Cadence Tempus

Job description

Job Description:

In this role, the Engineer will apply and lead Broadcom's proven design methodology and milestone flow to meet rigorous criteria for achieving Right-First-Time silicon. The STA Engineer is responsible for ensuring robust timing closure and signoff readiness for block- and full-chip designs across all modes and corners. This role owns timing constraint development and validation, performs detailed setup/hold and variation-aware analysis, and partners closely with Synthesis, CTS, Physical Design, and Design teams to debug violations and drive ECO-based optimizations through tape out.

Responsibilities include, but are not limited to:

• Perform full-chip and block-level Static Timing Analysis (STA) across all modes and corners.
• Analyze and debug setup, hold, recovery, removal, clock gating, and signal integrity-related timing violations.
• Work closely with Physical Design, Synthesis, CTS, and Design teams to achieve timing closure.
• Develop and maintain timing constraints including SDC creation, validation, and signoff readiness.
• Drive timing closure through ECO implementation and timing optimization.
• Analyze timing impact due to process, voltage, and temperature variations.
• Support timing signoff for pre-layout and post-layout stages.
• Perform cross-functional reviews for timing convergence and provide recommendations.
• Generate timing reports and communicate closure status to project stakeholders.

Minimum Qualifications:

• MSEE/MSCS with 10+ years of experience, or BSEE/BSCS with 12+ years of experience in Static Timing Analysis (STA) and timing closure for block and/or full-chip designs.
• Strong understanding of CMOS fundamentals, timing concepts, and semiconductor design flow.
• Hands-on experience in setup/hold analysis, path-based analysis, OCV/AOCV/POCV, derates, and MMMC concepts.
• Good understanding of clock tree, clock uncertainty, latency, skew, and jitter.
• Experience in timing constraints development and debugging.
• Strong knowledge of SDC, timing exceptions, false paths, multicycle paths, and case analysis.
• Familiarity with timing closure techniques and ECO methodologies.
• Hands-on experience with industry-standard STA tools such as Synopsys PrimeTime or Cadence Tempus.
• Good scripting skills in Tcl, Perl, or Python.
• Ability to analyze and resolve timing violations independently.
• Exposure to low-power timing analysis and UPF/CPF-aware STA.
• Familiarity with SI-aware timing, Crosstalk analysis, and IR-drop-aware timing closure.
• Knowledge of advanced technology nodes and variation-aware signoff methodologies.
• Exposure to automation and flow development.
• Experience in cross-functional collaboration with PD, RTL, and Signoff teams.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Welcome! Thank you for your interest in Broadcom! We are a global technology leader that designs, develops and supplies a broad range of semiconductor and infrastructure software solutions. For more information please visit our video library and check out our Connected by Broadcom series.

Follow us on Linked In Broadcom Inc.