Principal Physical Design Engineer - STA

Mulya Technologies; Hyderabad; On-site; INR 2,000,000 - 3,000,000; Full time

Job summary

A leading company in semiconductor design is seeking a Principal Physical Design Engineer specializing in Static Timing Analysis. The role involves developing and debugging timing constraints, performing noise analysis, and ensuring timing convergence for high-speed devices. Ideal candidates will have extensive experience in physical implementation and a strong track record in high-volume product delivery.

Qualifications

• 12+ years of experience with BSEE/CE or 10+ years with MSEE/CE.
• Proven track record of shipped high-volume products.
• Experience with timing closure in 7nm, 5nm, and/or 3nm processes.

Responsibilities

• Perform STA at block/full-chip level.
• Specify timing ECOs manually or via tools.
• Develop and debug timing constraints.

Skills

Proficiency in STA tools

Timing constraint verification

High-speed IO constraints

LVF/OCV variation methodologies

Timing derates implementation

Education

BSEE/CE or MSEE/CE

Tools

Tempus

Tweaker

PrimeTime

TimeVision

FishTail

Job description

Principal Physical Design Engineer - STA

Join a pioneering team at Mulya Technologies as a Static Timing Analysis Engineer. We are committed to revolutionizing AI compute systems and infrastructure with our innovative Accelerated Compute Fabric. Our experienced team focuses on developing scalable networking silicon and software, solving I/O bottlenecks in distributed AI and compute clusters.

Position: Full-Time, Experienced

Summary: We seek talented engineers with experience in physical implementation of large-scale networking and computing semiconductors, especially in static timing analysis. You will work on developing and debugging timing constraints, specifying timing ECOs, and ensuring timing convergence in complex, high-speed devices.

Responsibilities:

1. Perform STA at block/full-chip level
2. Specify timing ECOs manually or via tools
3. Perform noise analysis at chip level
4. Develop and debug timing constraints
5. Define and implement MCMM timing closure methodology
6. Drive hierarchical timing methodologies for full-chip timing closure

Skills & Qualifications:

• Proficiency in STA tools like Tempus, Tweaker, PrimeTime
• Experience with timing constraint verification tools like TimeVision or FishTail is a plus
• Experience with timing closure in 7nm, 5nm, and/or 3nm processes
• Experience with high-speed IO constraints such as SerDes and DDR
• Strong understanding of LVF/OCV variation methodologies
• Knowledge of timing convergence in multi-voltage scenarios
• Experience with timing derates and their implementation
• BSEE/CE with 12+ years or MSEE/CE with 10+ years of experience
• Proven track record of shipped high-volume products

Contact: Mining The Knowledge Community

Additional Details:

• Seniority Level: Mid-Senior level
• Employment Type: Full-time
• Job Functions: Research, Design, Engineering
• Industries: Hardware Manufacturing, Semiconductor, Software Development