IC design Engineer

Broadcom; Bengaluru; On-site; INR 3,000,000 - 5,000,000; Full time

Job summary

Broadcom in Bengaluru, India seeks an IC Design Engineer to lead and execute backend digital design flows for 5nm and below technologies. You will master P&R, routing, STA, and ECO processes, while constructing automation and improving turnaround times.

Applicants should demonstrate strong TCL/Perl, deep analytical skills, and cross-functional collaboration across global teams within a fast-paced environment. This role is based in Bengaluru with Broadcom’s renowned innovation culture.

Qualifications

• MSEE/MSCS 3+ years (BSEE/BSCS 5+ years)
• Deep understanding of backend digital design flow
• Proficient in timing constraints, physical constraints
• Proficient with backend EDA tools (Genus/Innovus/Quantus/Tempus, DC/Star-RCXT/PT, PrimeRail/Voltus, Redhawk)
• Proficiency in Tcl and Perl
• Excellent analytical skills
• Collaborates effectively in a multi-functional environment across sites/time zones

Responsibilities

• Understand SoC top-down/bottom-up physical design integration in 5nm and below technologies
• Master P&R flows and adapt internal flows for efficiency
• Implement timing and functional ECOs
• P&R, Extraction, PV; work toward STA closure
• Build automation flows or adapt existing ones for reuse
• Be proficient in Cadence/Synopsys/Mentor tools for P&R, PV, STA, ECO
• Automate using programming languages used in the industry
• Lead by example to improve throughput and quality
• Drive tangible improvements in turnaround time and quality

Skills

Tcl

Perl

Analytical

Collaboration

Education

MSEE/MSCS (BSEE/BSCS acceptable)

Tools

Genus

Innovus

Quantus

Tempus

DC/Star-RCXT/PT

PrimeRail/Voltus

Redhawk

Job description

IC Design Engineer

Job Description

In this role, the Engineer will apply and lead Broadcom's proven design methodology and milestone flow to meet Broadcom's rigorous criteria for achieving Right-first time silicon. Candidate should have very good experience in layout activities of block and level. Should be well experienced in floor-planning, partitioning, placement, clock tree synthesis, route and physical verification.

Responsibilities

• Understanding of SoC for top-down/bottom-up physical design integration in 5nm and lower technologies
• Must have deep functional knowledge of P&R flows, should be able to catch up quickly on internal flows, adapt.
• Implement timing and functional ECO
• P&R, Extraction, Physical verification, work towards STA closure
• Build automation flows wherever needed/adapt to existing flows for re-use
• Must be proficient in any of the Cadence/Synopsys/Mentor EDA tools for P&R, PV, STA, ECO
• Needs to be automation savvy with high expertise in one of the programming languages used in the industry
• Clearly know requisites for executing his/her job and lead by example
• Bring tangible improvement in TAT with better quality

Minimum Qualifications

• MSEE/MSCS 3+ years (BSEE/BSCS 5+ years)
• A deep understanding of backend digital design flow
• Proficient in timing constraints, physical constraints
• Proficient in handling EDA tools across floorplan/partition/placement/cts/route stages for SoC TOP.
• Proficient with backend EDA tools viz, Genus/Innovus/Quantus/Tempus, DC/Star-RCXT/PT, PrimeRail/Voltus, Redhawk
• Proficiency in Tcl and Perl
• Excellent analytical skills
• Shown ability to collaborate in a multi-functional environment, cross-site or cross-time zone

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Experience Level Mid Level