Sr. Staff Engineer PD

GlobalFoundries inc.; Bengaluru; On-site; INR 3,500,000 - 6,000,000; Full time

Job summary

GlobalFoundries inc. in Bengaluru, Karnataka, seeks a seasoned Physical Design Engineer to implement RTL-to-GDSII flows across SoCs.

You will execute synthesis, placement, CTS, PNR, timing, power analysis, and sign-off verification while driving design convergence with RTL, DFT, and package teams. You will automate flows using TCL, Python, or Perl, and apply reuse strategies to meet performance, area, and power targets on customer-specific ICs.

Qualifications

• 4+ years of hands-on physical design experience on SoCs (RTL-to-GDSII).
• Proficient with Synthesis, PNR, STA, and verification in EDA tools.
• Experience with scripting for automation (TCL, Python, Perl).
• Knowledge of MCMM, advanced nodes, IP integration.
• Strong cross-team communication and problem solving.

Responsibilities

• Deliver hands-on physical design and implement custom silicon solutions.
• Execute all phases of physical design: synthesis, floorplanning, placement, CTS, PNR, timing closure, power/noise analysis, signoff verification.
• Apply design strategies to meet performance, area, and power targets for customer-specific ICs.
• Reuse methodologies using standard IP blocks, libraries, and flows to accelerate projects.
• Resolve timing, congestion, and power issues in high-speed, high-density designs using EDA tools and scripting.
• Collaborate with RTL design, verification, DFT, and package teams to ensure design convergence.
• Perform physical verification (DRC, LVS) and support debug for clean tape-out deliverables.
• Automate flows with TCL, Python, or Perl; analyze metrics for process improvements.

Skills

Physical design

TCL/Python scripting

Analytical mindset

Education

Electrical/Computer Engineering

Tools

ICC2

Fusion Compiler

Innovus

Genus

Calibre

Job description

The Physical Design Engineer delivers hands-on expertise in designing and implementing custom silicon solutions to meet detailed customer requirements. This role executes physical design flows—including synthesis, place-and-route, and verification—while applying standardized methodologies for efficient IP reuse, rapid turnaround, and high-quality tape-outs.Your JobImplement DFT architectures including ATPG, MBIST, LBIST, scan insertion, and analog test features Execute all phases of physical design: synthesis, floorplanning, placement, clock tree synthesis, place-and-route, timing closure, power/noise analysis, and signoff verification.Implement design strategies to achieve performance, area, and power targets for customer-specific ICs under lead guidance.Apply re-use methodologies, leveraging standard IP blocks, libraries, and flows to accelerate project execution.Resolve timing, congestion, and power issues in high-speed, high-density designs using EDA tools and scripting.Collaborate with RTL design, verification, DFT, and package teams to integrate requirements and ensure design convergence.Perform physical verification (DRC, LVS) and support debug for clean tape-out deliverables.Automate flows with TCL, Python, or Perl scripts to improve productivity and repeatability.Analyze design metrics and contribute to process improvements through data-driven insights.Other ResponsibilitiesPerform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs.Required QualificationsBachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.4+ years of hands-on physical design experience on SoCs, covering RTL-to-GDSII flows.Proficiency with EDA tools like Synopsys ICC2/Fusion Compiler, Cadence Innovus/Genus, or Mentor Calibre for synthesis, PNR, STA, and verification.Strong knowledge of STA (PrimeTime/Tempus), power analysis, and congestion mitigation techniques.Experience with scripting (TCL, Python, Perl) for flow automation and debugging.Familiarity with advanced nodes, multi-corner multi-mode (MCMM) analysis, and IP integration.Analytical mindset for tackling complex timing/power challenges and effective cross-team communication.Preferred QualificationsExperience with custom silicon for automotive, high-performance computing, or AI applications.Proactive in adopting new tools, flows, and best practices for re-use and efficiency.Detail-oriented team player committed to quality and on-time delivery.Information about our benefits you can find here: https://gf.com/about-us/careers/opportunities-asia