Physical Design Engineer

Acesoft Labs; Hyderabad; On-site; INR 1,200,000 - 2,400,000; Full time

Job summary

Acesoft Labs in Hyderabad seeks an experienced physical design engineer to drive RTL2GDS implementations, tapeouts, and timing closure. You will work with Innovus and Tempus, handle 7nm/6nm/5nm flows, and optimize partitions and memory-dominated designs.

Candidates should have 5–15 years of hands-on PV, CTS, STA experience, and scripting in Tcl/Tk/Perl.

Qualifications

• 5–15 years of experience in physical design
• Hands-on in RTL2GDS flows and signoff
• Strong knowledge of timing closure and STA
• Experience with high-frequency partitions and memory-heavy designs
• Proficient in Tcl/Tk/Perl scripting

Responsibilities

• Execute physical design flows from synthesis to tapeout
• Ensure timing closure and signoff for complex designs
• Collaborate with DV/DFT and backend teams
• Optimize partitions for high-frequency and memory-dominated blocks

Skills

RTL2GDS implementation

Timing closure

Partitioning high freq

Memory-dominated designs

Tcl/Perl scripting

Tools

Innovus

Tempus

Job description

• Experience on RTL2GDS Implementation i.e. Synthesis, Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification.
• Should have experience on Physical Design Methodologies and lower tech nodes like 7nm, 6nm & 5nm.
• Should have experience in handling high frequency partitions & memory dominated designs.
• Should have experience on programming in Tcl/Tk/Perl.
• Well versed with timing constraints, STA and timing closure.
• Should have worked on minimum 3 tapeouts.
• Should have hands-on experience on Hierarchical level PV & signoff closure
• Tools: Innovus, Tempus
• Experience Range : 5 - 15 years
• Primary Skills : Physical Design, CTS, STA & Physical Verification.