Physical Design Engineer

Acesoft Labs; Bengaluru; On-site; INR 2,600,000 - 5,200,000; Full time

Job summary

Acesoft Labs is seeking an experienced Physical DesignEngineer to work on RTL2GDS flows, including synthesis, floorplanning and placement, CTS, routing, and STA. The role requires hands-on PV and signoff closure for advanced nodes.

Ideal candidates have 5–15 years of experience, strong timing knowledge, and exposure to 7nm/6nm/5nm processes. You'll work on high-frequency designs with memory components and use Innovus/Tempus tools in a dynamic team.

Qualifications

• Experience in RTL2GDS flow covering Synthesis, Floorplanning, Placement, CTS, Routing, STA, and Power Integrity Analysis.
• Strong understanding of physical design methodologies for 7nm/6nm/5nm nodes.
• Experience handling high frequency partitions and memory-dominated designs.

Skills

Physical Design

CTS

STA

Physical Verification

Tools

Innovus

Tempus

Job description

• Experience on RTL2GDS Implementation i.e. Synthesis, Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification.
• Should have experience on Physical Design Methodologies and lower tech nodes like 7nm, 6nm & 5nm.
• Should have experience in handling high frequency partitions & memory dominated designs.
• Should have experience on programming in Tcl/Tk/Perl.
• Well versed with timing constraints, STA and timing closure.
• Should have worked on minimum 3 tapeouts.
• Should have hands-on experience on Hierarchical level PV & signoff closure
• Tools: Innovus, Tempus
• Experience Range : 5 - 15 years
• Primary Skills : Physical Design, CTS, STA & Physical Verification.