Physical Design Engineer

TalentRabbit; Bengaluru; On-site; INR 900,000 - 1,300,000; Full time

Job summary

TalentRabbit is seeking talented Physical Design Engineers in Bengaluru to contribute to RTL-to-GDSII implementation and physical design activities. The role involves floorplanning, CTS, routing, and timing closure within semiconductor design flows.

You will collaborate with RTL, DFT, synthesis, and sign-off teams to achieve design closure, perform STA, and optimize power, performance, and area in a dynamic engineering environment.

Qualifications

• Hands-on RTL-to-GDSII implementation experience.
• Experience with floorplanning, placement, CTS, routing, and timing closure.
• Proficient in STA and timing constraints (SDC).

Responsibilities

• Perform RTL-to-GDSII implementation and physical design activities.
• Work on floorplanning, power planning, placement, CTS, routing, and physical verification.
• Perform static timing analysis (STA), timing closure, and design optimization.
• Analyze and resolve setup/hold violations, congestion, and signal integrity issues.
• Work on power, performance, and area (PPA) optimization.
• Run design checks such as DRC, LVS, and electrical rule checks as applicable.
• Collaborate with RTL, DFT, synthesis, and sign-off teams to achieve design closure.

Skills

VLSI fundamentals

RTL-to-GDSII flow

Floorplanning & CTS

STA & timing closure

EDA tools proficiency

Job description

We are looking for talented and motivated Physical Design Engineers to join our growing semiconductor engineering team. Candidates with hands-on experience in RTL-to-GDSII implementation, timing optimization, and physical design flows are encouraged to apply.

Key Responsibilities

• Perform RTL-to-GDSII implementation and physical design activities.
• Work on floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and physical verification.
• Perform static timing analysis (STA), timing closure, and design optimization.
• Analyze and resolve setup/hold violations, congestion, and signal integrity issues.
• Work on power, performance, and area (PPA) optimization.
• Run design checks such as DRC, LVS, and electrical rule checks as applicable.
• Collaborate with RTL, DFT, synthesis, and sign-off teams to achieve design closure.

Required Technical Skills

• Strong understanding of VLSI fundamentals, CMOS concepts, and digital design.
• Knowledge of the RTL-to-GDSII physical design flow.
• Hands-on experience with floorplanning, placement, CTS, routing, and timing closure.
• Knowledge of Static Timing Analysis (STA), setup/hold analysis, and timing constraints (SDC).
• Familiarity with industry-standard EDA tools such as Synopsys ICC2, Fusion Compiler, PrimeTime, Cadence Innovus, or Tempus.
• Understanding of physical verification, including DRC and LVS.
• Strong debugging, analytical, and problem-solving skills.

Experience Levels

• 1-3 Years: Hands-on experience in physical design implementation, timing analysis, and basic PPA optimization.
• 3-5 Years: Experience in placement, CTS, routing, timing closure, and resolving implementation challenges.
• 5-7 Years: Strong expertise in end-to-end physical design, advanced timing closure, congestion analysis, and PPA optimization.