Staff Engineer, Physical Design

SiFive; Bengaluru; On-site; INR 2,500,000 - 4,500,000; Full time

Job summary

PVH in Bengaluru seeks a Staff Physical Design Engineer to drive physical design implementation, timing closure, and the structural backbone of next‑gen designs. You will translate RTL into silicon, analyze layout vs circuit behavior, and ensure long-wire signal distribution and clocking networks meet performance targets.

You will collaborate with RTL and architecture teams to optimize CTS, manage interconnect routing, and mentor junior engineers while advancing design methodologies and flows.

Qualifications

• 8+ years of hands-on physical design experience with tape-outs on advanced nodes.
• Deep familiarity with physical implementation of clocking structures and interconnect routing.
• Strong fundamentals in CMOS, RC delay networks, and timing/noise concepts.
• Proficiency with industry-standard EDA tools (Fusion Compiler, PrimeTime, Innovus, Tempus).
• Ability to debug timing violations, crosstalk delay, and IR drop issues.

Responsibilities

• Advanced Clock Distribution & Circuit Design: architect high-speed, low-skew clock networks (mesh, H-tree, hybrid topologies).
• Interconnect Physical Design: manage global signal planning, high-speed routing, and repeater insertion strategies.

Skills

8+ years physical design

Clock distribution design

VLSI fundamentals

EDA tools: Synopsys/Cadence

Debug timing & noise

Education

Bachelor’s or Master’s degree in Electrical Engineering

Tools

Synopsys Fusion Compiler

Synopsys PrimeTime

Cadence Innovus

Cadence Tempus

Job description

About the Role

As a Staff Physical Design Engineer, you will be a key technical contributor driving the physical design implementation, timing closure, and structural backbone of our next-generation designs. In this role, your primary focus will be mastering the critical intersection of global signal planning, advanced clocking architectures, and high-performance physical design interconnects. You will be responsible for translating complex RTL into high-performance silicon implementations by analyzing the design from both a physical layout and a circuit-level perspective—ensuring that long-wire signal distribution and clocking networks inherently support robust electrical performance.

We are looking for a "full-stack" physical design engineer who understands that chip performance relies heavily on efficient distribution networks. You should be the type of engineer who enjoys diving into schematics and microarchitecture to understand how clocking choices impact PPA, how global wire parasitics affect latency, and how transistor-level behavior influences chip-level signal and timing integrity.

Key Responsibilities – What you’ll do

• Advanced Clock Distribution & Circuit Design: Architect and implement high-speed, low-skew clock distribution networks (e.g., mesh, H-tree, hybrid topologies). Apply circuit-level understanding to optimize clock buffers, clock gaters, latches, and multi-source CTS.
• Interconnect Physical Design: Manage the physical implementation of global signal planning, including high-speed bus routing, long-wire interconnect span limits, and repeater insertion strategies. Optimize long interconnect paths to mitigate RC delay, wire resistance variations, and routing congestion.
• Circuit-Level Timing & Noise Integrity: Leverage a strong fundamental grasp of RC interconnect modeling and transistor-level behavior to resolve deep-submicron physical effects—such as crosstalk delay, Electromigration (EM), and dynamic IR‑drop on clock and global signal lines.
• Architectural & Circuit Co‑Optimization: Partner with RTL and Architecture teams to influence design decisions. Bridge the gap between logic design and circuit reality, identifying bottlenecks early (such as asynchronous clock domain crossings and interconnect span limits) and suggesting structural or microarchitectural optimizations.
• Technical Leadership & Signoff: Act as the subject matter expert for interconnect structures, clock planning, and circuit techniques during implementation. Mentor junior engineers and contribute to the evolution of advanced design methodologies and flows.

Requirements – What you’ll bring

• 8+ years of hands‑on physical design experience with a proven track record of successful tape‑outs on advanced process nodes (7nm and below preferred).
• Deep familiarity with the physical implementation of advanced clocking structures, global interconnect routing, multi‑corner multi‑mode (MCMM) timing closure, and jitter analysis.
• Strong fundamentals in VLSI design, including CMOS circuit behavior, RC delay networks and transistor-level timing/noise concepts.
• Expert‑level proficiency with industry‑standard EDA tools—specifically Synopsys (Fusion Compiler, PrimeTime) and/or Cadence (Innovus, Tempus) implementation and sign‑off tools, with heavy emphasis on CTS, parasitic extraction (RC), and Static Timing Analysis (STA) engines.
• Ability to debug complex timing violations, cross‑talk delay, global interconnect routing congestion, and transient IR drop issues with minimal supervision.
• Bachelor’s or Master’s degree in ...