Physical Design Engineer

Lancesoft; Hyderabad, Chennai, Bengaluru; On-site; INR 900,000 - 1,300,000; Full time

Job summary

Lancesoft is seeking an experienced VLSI Engineer for Physical Design, STA and Synthesis, with hands-on Cadence Innovus in our Bangalore/Hyderabad/Chennai teams. You will drive RTL-to-GDSII flows, floorplanning, CTS, routing, and timing closure to meet PPA targets.

Ideal candidates have 4+ years in VLSI Physical Design, expertise in STA and synthesis, and scripting skills in Tcl or Python to automate flows. Join a collaborative design team delivering high-quality silicon.

Qualifications

• 4+ years of experience in VLSI Physical Design, STA, and/or Synthesis.
• Hands-on Cadence Innovus for physical implementation.
• Strong RTL synthesis understanding and RTL-to-GDSII flow.
• Experience with Static Timing Analysis and timing closure.
• Familiarity with EDA tools and Tcl/Python scripting.

Responsibilities

• Perform RTL-to-GDSII implementation, including floorplanning, placement, CTS, routing, and physical verification.
• Execute synthesis, timing analysis, and design optimization to meet PPA targets.
• Perform STA, including setup and hold analysis, timing closure, and timing violation debugging.
• Work on timing optimization, congestion analysis, and PPA improvements.
• Handle timing constraints, including SDC creation and validation.
• Analyze and resolve timing issues across different PVT corners and modes.
• Collaborate with RTL, synthesis, physical design, and signoff teams to ensure design closure.

Skills

VLSI Physical Design

STA & Synthesis

RTL-to-GDSII flow

Timing analysis

Scripting (Tcl/Python)

Tools

Cadence Innovus

Job description

Job Description: Physical Design / STA & Synthesis Engineer

Experience: 4+ Years
Location: Bangalore / Hyderabad / Chennai
Notice Period: Immediate to 30 Days Preferred

Job Overview

We are looking for experienced VLSI Engineers with expertise in Physical Design, Static Timing Analysis (STA), and Synthesis. Candidates should have hands‑on experience with Cadence Innovus and a strong understanding of RTL-to-GDSII implementation flow.

Key Responsibilities

• Perform RTL-to-GDSII implementation, including floorplanning, placement, clock tree synthesis (CTS), routing, and physical verification.
• Execute synthesis, timing analysis, and design optimization to meet PPA targets.
• Perform Static Timing Analysis (STA), including setup and hold analysis, timing closure, and timing violation debugging.
• Work on timing optimization, congestion analysis, and power, performance, and area (PPA) improvements.
• Handle timing constraints, including SDC creation and validation.
• Analyze and resolve timing issues across different PVT corners and modes.
• Collaborate with RTL, synthesis, physical design, and signoff teams to ensure successful design closure.

Required Technical Skills

• 4+ years of experience in VLSI Physical Design, STA, and/or Synthesis.
• Hands‑on experience with Cadence Innovus for physical implementation.
• Strong understanding of RTL synthesis and the RTL-to-GDSII flow.
• Experience with Static Timing Analysis, setup/hold checks, and timing closure.
• Knowledge of floorplanning, placement, CTS, routing, and physical design optimization.
• Experience with timing constraints, SDC, and timing reports.
• Familiarity with industry-standard EDA tools and scripting using Tcl or Python.