Physical Design Engineer

SEMIENG; Bengaluru; On-site; INR 900,000 - 1,400,000; Full time

Job summary

SEMIENG Semiconductors Solutions OPC Private Limited in Bengaluru seeks Physical Design Engineers with 3+ years of ASIC/SoC experience to drive physical implementation and sign-off.

You will perform floorplanning, CTS, routing, STA, EMIR, and power integrity analyses, ensuring timing closure across MMMC scenarios. Join us to contribute to next-generation semiconductor designs in a dynamic team environment.

Qualifications

• Experience in ASIC/SoC physical implementation and sign-off.
• Hands-on with STA, EMIR, and power integrity analysis.
• Familiar with poly/metal routing and sign-off flows.

Responsibilities

• Execute block-level physical design activities from netlist to GDSII.
• Perform floorplanning, power planning, placement, CTS, and routing.
• Conduct STA timing closure and MMMC timing analysis.
• Perform static and dynamic IR drop analyses and power integrity optimization.
• Work on multi-mode multi-corner timing analysis.
• Resolve timing, congestion, and fanout issues; support PPA optimization.
• Perform DRC, LVS, and antenna checks.

Skills

Physical Design

STA

EMIR

Timing Closure

Education

BE/B.Tech in Electronics/Electrical/VLSI

ME/MTech

Tools

Innovus

ICC2/Fusion Compiler

PrimeTime

Tempus

RedHawk-SC

Voltus

Job description

SEMIENG is Hiring | Physical Design Engineers - VLSI

Location: Bengaluru (Bangalore)

Experience: 3+ Years

Company: SEMIENG Semiconductors Solutions OPC Private Limited

We are looking for skilled Physical Design Engineers with hands‑on experience in ASIC/SoC physical implementation, Static Timing Analysis (STA), Electromigration & IR Drop (EMIR), and Physical Design sign-off.

Website: www.semieng.in

Key Responsibilities

• Execute block-level physical design activities from netlist to GDSII.
• Perform floorplanning, power planning, placement, Clock Tree Synthesis (CTS), and routing.
• Conduct STA, including setup/hold analysis, timing optimization, and timing closure.
• Perform static and dynamic IR Drop analysis, electromigration analysis, and power integrity optimization.
• Work on multi-mode multi-corner (MMMC) timing analysis.
• Resolve timing violations, congestion, transition, capacitance, and fanout issues.
• Support PPA optimization, ECO implementation, and physical sign-off.
• Perform DRC, LVS, and antenna checks.

Required Technical Skills

• Physical Design: Floorplanning, Placement, CTS, Routing, PnR, Timing Closure.
• STA: Setup/Hold, SDC, OCV/AOCV/POCV, MMMC.
• EMIR: Static/Dynamic IR Drop, Electromigration, Power Grid Analysis.
• EDA Tools: Innovus, ICC2/Fusion Compiler, PrimeTime, Tempus, RedHawk-SC, Voltus (experience with relevant tools).
• Scripting: TCL, Python, Perl, or Shell.

Preferred Qualifications

• B.E./B.Tech/M.E./M.Tech in Electronics, Electrical, VLSI, or related disciplines.
• 3+ years of relevant Physical Design experience.
• Exposure to advanced technology nodes and low-power design methodologies is an advantage.
• Strong debugging and analytical skills.

Join SEMIENG and contribute to next-generation semiconductor engineering.

SEMIENG | Engineering your success.

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