Physical Design Engineer

Coventine Digital Private Limited; Bengaluru; On-site; INR 2,626,970 - 4,378,283; Full time

Job summary

A leading company in semiconductor manufacturing seeks a Physical Design Engineer in Bengaluru. The role requires expertise in physical design tasks including timing closure and automation skills. Candidates should possess a BE/BTECH/MTECH in EE/ECE and have experience with EDA tools. This mid-senior level position offers a chance to work on cutting-edge technology in a dynamic environment.

Qualifications

• Deep understanding of synthesis, place & route, CTS, and timing convergence.
• Experience in lower tech nodes (3nm, 5nm, 7nm).
• Good knowledge of DRC, LVS, ERC, and PERC rule files.

Responsibilities

• Responsible for planning and execution of physical design tasks.
• Take ownership of Block/sub-system execution cycle.
• Participate in all stages of design including floor planning and physical verification.

Skills

Timing closure

Automation skills

Out-of-the-box thinking

Education

BE/BTECH/MTECH in EE/ECE

Tools

EDA tools and flows

Perl

TCL

Fusion compiler-based RTL2GDS flow

Job description

Should be able to handle Full chip PnR (timing/congestion/CTS issues), understanding of IO ring, package support, multi voltage design.

Deep understanding of the concepts related to synthesis, place & route, CTS, timing convergence, IR/EM checks, and signoff DRC/LVS closure.

Responsible for independent planning and execution of all aspects of physical design, including floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM.

Must have participated in all stages of the design (floor planning, placement, CTS, routing, physical verification, IREM).

Well versed with the timing closure (STA) and timing closure methodologies.

Good understanding of DRC, LVS, ERC, and PERC rule files for lower tech node layout verification.

Experience in lower tech nodes (3nm, 5nm, 7nm).

Good automation skills in PERL, TCL, and EDA tool-specific scripting.

Able to take complete ownership of Block/sub-system for the complete execution cycle. Out-of-the-box thinking to meet tighter PPA requirements.

Detailed knowledge of EDA tools and flows; Fusion compiler-based RTL2GDS flow is desired.

Tools:

• EDA tools and flows, Perl, TCL, Fusion compiler-based RTL2GDS flow.

Qualification:

• BE/BTECH/MTECH in EE/ECE.

Seniority level

• Mid-Senior level

Employment type

• Full-time

Job function

• Industries: Semiconductor Manufacturing and IT Services and IT Consulting

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