Physical Design Engineer (Trained Intern) -- Bangalore

Technologies Pvt Ltd; Bengaluru; On-site; INR 200,880 - 267,840; Full time

Job summary

Technologies Pvt Ltd in Bengaluru is seeking a Physical Design Engineer (Trained Intern) to perform ASIC physical design tasks from synthesis handoff to GDSII generation. You will execute floor planning, CTS, routing, and physical optimization, while supporting timing closure and signoff activities.

As a fresher, you will collaborate with RTL, verification, and DFT teams, gaining exposure to process technologies like SKY130 and PD Ks, with Linux scripting and debugging skills as an advantage.

Qualifications

• Strong understanding of the ASIC Physical Design flow.
• Hands-on knowledge of OpenROAD and OpenLane tools, or interest to work with them.
• Exposure to semiconductor process technologies or PD Ks such as SKY130.
• Basic understanding of floor planning, placement, CTS, routing, STA, and physical verification.
• Familiarity with Linux and scripting (Tcl/Shell/Python) is an advantage.
• Excellent analytical and debugging skills.

Responsibilities

• Perform ASIC physical design tasks from synthesis handoff to GDSII generation.
• Execute floor planning, placement, CTS, routing, and physical optimization.
• Support timing closure and resolve setup/hold violations.
• Perform DRC/LVS checks and assist in physical signoff activities.
• Generate and validate GDSII for tape-out.
• Work closely with RTL, verification, and DFT teams to meet goals.
• Continuously learn and adopt new tools, methodologies, and processes.

Skills

ASIC physical design flow

Analytical & debugging skills

Self-motivated learner

Education

Bachelor's/Master's in relevant field

Tools

OpenROAD

OpenLane

Linux

Tcl/Shell/Python scripting

Job description

Physical Design Engineer (Trained Intern)

Experience : Fresher

Education : B.E, M.E, M.Tech, B.Tech

Role :

Key Responsibilities

Perform ASIC physical design tasks from synthesis handoff to GDSII generation.

Execute floor planning, placement, clock tree synthesis (CTS), routing, and physical optimization.

Support timing closure and resolve setup/hold violations.

Perform DRC/LVS checks and assist in physical signoff activities.

Generate and validate GDSII for tape-out.

Work closely with RTL, verification, and DFT teams to achieve implementation goals.

Continuously learn and adopt new tools, methodologies, and process technologies.

Required Skills & Qualifications

Strong understanding of the ASIC Physical Design flow.

Hands-on knowledge of Open ROAD and Open Lane tools, or a strong interest in working with them.

Exposure to one or more semiconductor process technologies or PD Ks such as:

SKY130

SCL180

TSMC

Basic understanding of floor planning, placement, CTS, routing, STA, and physical verification.

Familiarity with Linux and basic scripting (Tcl/Shell/Python) is an advantage.

Excellent analytical and debugging skills.

Preferred Attributes

Self-motivated with a strong willingness to learn independently.

Demonstrated ability to pick up new technologies and solve technical challenges through self-learning.

Good communication and teamwork skills.

Passion for semiconductor design and continuous technical growth.

Job Description :

We are seeking enthusiastic and self-driven Physical Design Engineers who are passionate about VLSI implementation and ASIC design . Candidates should have hands-on exposure to the physical design flow and be eager to work with both open-source and commercial EDA tools.

The ideal candidate should have practical exposure to the complete physical design flow, including floor planning, placement, clock tree synthesis (CTS), routing, timing closure, physical verification, and successful GDSII generation.

The candidate should be capable of working independently as well as collaboratively within a design team.