Physical Design Engineer

eInfochips (An Arrow Company); Hyderabad; On-site; INR 2,500,000 - 4,000,000; Full time

Job summary

A semiconductor company is seeking a Lead Talent Acquisition professional in Hyderabad, Telangana, India. The ideal candidate will have over 5 years of experience in ASIC/SoC physical design, proficiency with Cadence tools, and the ability to mentor junior team members. The role involves hands-on design and verification tasks, project management, and ensuring design integration correctness. The company offers a full-time position at a mid-senior level.

Qualifications

• Minimum 5+ years of experience in ASIC/SoC physical design.
• Experience with advanced FinFET node designs.
• Proficiency with Cadence PnR/STA tools and Calibre; strong scripting/automation skills are a must.

Responsibilities

• Perform hands-on physical design and verification tasks across projects.
• Manage project-specific ASIC development flow setup and maintenance.
• Conduct floor-planning, place & route, CTS, timing closure, and IR/EM analysis.
• Create setup and scripts for DRC, LVS, DFM, and density checks.
• Ensure correct IP and pad-ring integration in designs.
• Mentor junior PD/PV team members and oversee their tasks.
• Report to the ASIC Design Director.

Skills

ASIC/SoC physical design

FinFET node designs

Cadence PnR/STA tools

Scripting/Automation

Education

B.Tech/M.Tech in Electronics Engineering

Tools

Cadence PnR/STA

Calibre

Job description

Lead Talent Acquisition @ eInfochips | VLSI Hiring Expert | Always on a lookout for smart folks in Semiconductor Tech roles

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Responsibilities

• Perform hands‑on physical design and verification tasks across projects in advanced process nodes.
• Manage project‑specific ASIC development flow setup and maintenance.
• Conduct floor‑planning, place & route, CTS, timing closure, IR/EM analysis, and LEC for block‑level and full‑chip designs; coordinate‑chip physical design and verification activities.
• Create setup and scripts for DRC, LVS, DFM, antenna and density checks; generate reports, debug, and implement fixes in the physical design database.
• Ensure correct IP and pad‑ring integration in block and flat designs.
• Mentor junior PD/PV team members and oversee their tasks.
• Report to the ASIC Design Director.

Qualifications

• Minimum 5+ years of experience in ASIC/SoC physical design.
• Experience with advanced FinFET node designs.
• Proficiency with Cadence PnR/STA tools and Calibre; strong scripting/automation skills are a must.
• B.Tech/M.Tech in Electronics Engineering.

Seniority Level

• Mid‑Senior level

Employment Type

• Full‑time

Job Function

• Semiconductor Manufacturing

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