Physical Design Engineer

ACL Digital; Bengaluru; On-site; INR 900,000 - 1,300,000; Full time

Job summary

ACL Digital in Bengaluru invites Senior & Lead Physical Design Engineers to join a team tackling complex ASIC challenges. You will own end-to-end Place & Route flows, floorplanning, CTS, routing for advanced nodes, and drive timing closures with strong SI fixes.

We value hands-on experience with DRC/LVS/ERC, IR drop analysis, and proficiency in Innovus, PrimeTime, and Calibre. Bring 5–12 years of physical design expertise and a collaborative spirit to push silicon success.

Qualifications

• 5–12 years of relevant experience in physical design.
• Hands-on experience with end-to-end PnR flows and silicon signoff.

Responsibilities

• Execute end-to-end Place & Route flow from Netlist to GDSII.
• Perform Floorplanning, CTS, placement, and routing for advanced nodes.
• Drive timing closure with STA, setup/hold, and SI fixes.
• Conduct physical verification (DRC, LVS, ERC) and IR drop analysis.
• Utilize industry-standard EDA tools (Innovus, Fusion Compiler, IC Compiler II, PrimeTime, Calibre).

Skills

End-to-end PnR flow

Floorplanning & CTS

Timing & Closure

Verification

Tools proficiency

Tools

Innovus

Fusion Compiler

IC Compiler II

PrimeTime

Calibre

Job description

We are Hiring: Senior & Lead Physical Design Engineers!

Looking to take on complex, sub-node ASIC challenges with an industry-leading team? ACL Digital is expanding its VLSI team in Bengaluru! We are seeking high-caliber Physical Design Engineers with strong hands-on expertise in complete PnR flows to design next-generation silicon.

Key Highlights:

• Experience: 5 to 12 Years
• Company: ACL Digital

Role Responsibilities & Key Skills:

• Core Expertise: End-to-end Place & Route (PnR) flow execution from Netlist to GDSII.
• Floorplanning & CTS: Expertise in Floorplanning, Power Grid Design, Placement, Clock Tree Synthesis (CTS), and Routing on lower technology nodes
• Timing & Closure: Strong background in Static Timing Analysis (STA), setup/hold timing closure, and SI (Signal Integrity) fixes.
• Verification: Hands-on experience with Physical Verification (DRC, LVS, ERC, Antenna) and IR Drop Analysis (RedHawk/Voltus).
• Tools: Proficiency with industry-standard EDA tools (Innovus / Fusion Compiler/IC Compiler II, PrimeTime, Calibre).