Physical Design Engineer

Weekday; Bengaluru; On-site; INR 3,000,000 - 7,500,000; Full time

Job summary

Weekday in Bengaluru is seeking a seasoned Physical Design Engineer to join its VLSI/ASIC team. The candidate should have 6–15 years of hands-on experience in physical design, with strong Cadence Innovus expertise and STA knowledge.

The role focuses on driving designs from netlist to GDSII, ensuring timing closure, power integrity, and design robustness. Responsibilities include end-to-end physical design activities, analysis of timing reports, and collaboration with RTL, synthesis, and

Qualifications

• 6–15 years of hands‑on experience in Physical Design / ASIC implementation.
• Strong expertise in Cadence Innovus and experience using it across the physical implementation flow.
• Strong understanding and practical experience with Static Timing Analysis (STA) and timing closure.
• Solid knowledge of the complete physical design flow from netlist to GDSII.
• Strong understanding of floorplanning, power planning, placement, CTS, routing, optimization, and physical verification.
• Experience debugging setup/hold violations and resolving timing and congestion issues.

Responsibilities

• Perform end-to-end physical design activities including floorplanning, power planning, placement, CTS, routing, optimization, and physical verification.
• Develop and implement physical design strategies for complex digital blocks and full-chip designs.
• Use Cadence Innovus extensively for placement, CTS, routing, timing optimization, and design closure.
• Analyze timing reports and perform STA to identify setup and hold violations and drive timing closure.
• Work on congestion analysis, placement optimization, buffering, cell sizing, and other techniques to improve PPA and timing.
• Perform clock-tree analysis and optimization to manage skew, latency, transition, and clock-related constraints.
• Collaborate with synthesis and RTL teams to resolve timing, area, power, and physical‑design challenges.
• Debug implementation issues and develop effective solutions to achieve design goals within schedule and PPA constraints.
• Review and validate design constraints, timing exceptions, clock definitions, and implementation quality.
• Support physical sign‑off activities and ensure designs meet required performance, power, and reliability targets.
• Participate in methodology improvements, automation, flow development, and physical design optimization initiatives.

Skills

ASIC implementation

Cadence Innovus

STA

Netlist to GDSII

Floorplanning

CTS

Timing closure

Tcl/Python

Flow automation

Education

Bachelor’s or Master’s degree in Electronics/Electrical/VLSI/Microelectronics

Tools

Cadence tools

STA tools

Scripting (Tcl/Python)

Job description

This role is for one of our clients

Industry: Semiconductors

Seniority level: Mid-Senior level

Min Experience: 6+ years

Location: Bengaluru
JobType: full-time

₹30,00,000 - ₹75,00,000 a year

We are seeking an experiencedPhysical Design Engineerwith6–15 years of industry experienceto join our VLSI/ASIC engineering team. The ideal candidate will have strong hands‑on expertise across the physical implementation flow, with particular emphasis onCadence InnovusandStatic Timing Analysis (STA). You will be responsible for taking designs from netlist through physical implementation, optimization, timing closure, and sign‑off while working closely with RTL, synthesis, STA, and verification teams.

Requirements

Key Responsibilities

• Perform end-to-end physical design activities includingfloorplanning, power planning, placement, clock tree synthesis (CTS), routing, optimization, and physical verification.
• Develop and implement physical design strategies for complex digital blocks and full-chip designs.
• UseCadence Innovusextensively for placement, CTS, routing, timing optimization, and design closure.
• Analyze timing reports and performSTAto identify setup and hold violations and drive timing closure.
• Work on congestion analysis, placement optimization, buffering, cell sizing, and other techniques to improve PPA and timing.
• Perform clock-tree analysis and optimization to manage skew, latency, transition, and clock-related constraints.
• Collaborate with synthesis and RTL teams to resolve timing, area, power, and physical‑design challenges.
• Debug implementation issues and develop effective solutions to achieve design goals within schedule and PPA constraints.
• Review and validate design constraints, timing exceptions, clock definitions, and implementation quality.
• Support physical sign‑off activities and ensure designs meet required performance, power, and reliability targets.
• Participate in methodology improvements, automation, flow development, and physical design optimization initiatives.

Must-Have Skills

• 6–15 years of hands‑on experience in Physical Design / ASIC implementation.
• Strong expertise inCadence Innovusand experience using it across the physical implementation flow.
• Strong understanding and practical experience withStatic Timing Analysis (STA)and timing closure.
• Solid knowledge of the complete physical design flow fromnetlist to GDSII.
• Strong understanding of floorplanning, power planning, placement, CTS, routing, optimization, and physical verification.
• Experience debugging setup/hold violations and resolving timing and congestion issues.
• Good understanding of multi-mode, multi-corner (MMMC) implementation and timing constraints.
• Familiarity with physical design challenges related to advanced semiconductor process nodes.
• Strong scripting/automation skills usingTcl, Python, or Shellare desirable for flow automation and analysis.

Good-to-Have Skills

• Experience withEMIR (Electromigration and IR Drop) analysisand power integrity considerations.
• Exposure to IR-drop analysis, electromigration checks, and power‑grid optimization.
• Experience working with physical sign‑off tools and methodologies.
• Knowledge of industry‑standard physical verification and sign‑off flows.
• Experience with low-power design methodologies and power optimization.
• Exposure to advanced-node designs and complex SoC implementation.

Education

Bachelor’s or Master’s degree inElectronics Engineering, Electrical Engineering, VLSI, Microelectronics, or a related discipline.