Hardware Design Engineer2

Sunrise Biztech Systems; Bengaluru; On-site; INR 1,500,000 - 3,000,000; Full time

Job summary

Sunrise Biztech Systems Pvt. Ltd. in Bengaluru is seeking a Physical Design Engineer with 4+ years of experience in ASIC implementation and RTL-to-GDSII flow.

The role focuses on end-to-end P&R at block/subsystem level and involves timing closure, constraints debugging, and ECO implementation. The candidate will work with multi-power domain designs, develop automation scripts in Tcl/Python/Perl, and optimize timing, power, and congestion to achieve design closure.

Qualifications

• 4+ years Physical Design / P&R
• RTL-to-GDSII
• Timing Closure & Constraints Debug
• Advanced-node experience (7nm/5nm/4nm/3nm/2nm)
• Innovus / ICC2 / Fusion Compiler
• Tcl/Python/Perl scripting
• Multi-power domain
• ECO implementation

Responsibilities

• Execute end-to-end P&R at Block/Subsystem level.
• Hands-on experience in Synthesis, Floorplanning, Placement, CTS, Routing, Timing Closure, and ECO.
• Work with multi-power domain designs and debug timing constraints.
• Develop implementation recipes and automation using Tcl/Python/Perl.
• Optimize timing, power, performance, and congestion.
• Collaborate with cross-functional teams to achieve design closure.

Skills

Physical Design

P&R

RTL-to-GDSII

Timing Closure

Constraints Debug

Scripting Tcl/Python/Perl

Multi-power domain

ECO implementation

Tools

Innovus

ICC2

Fusion Compiler

Job description

Urgent Hiring!!!

Greetings from Sunrise Biztech Systems Pvt. Ltd.

We are hiring for one of our reputed clients for the following position.

If you're interested and your experience matches the requirement, we'd love to hear from you.

Position: Hardware Design Engineer 29(2344-1)
Experience: 4 - 7 Years

Location: Bengaluru

Contract tenure: 12 months

Physical Design Engineer P&R

We are looking for a Physical Design Engineer with 4+ years of experience in ASIC implementation and RTL-to-GDSII flow.

Key Responsibilities

• Execute end-to-end P&R at Block/Subsystem level.
• Hands-on experience in Synthesis, Floorplanning, Placement, CTS, Routing, Timing Closure, and ECO.
• Work with multi-power domain designs and debug timing constraints.
• Develop implementation recipes and automation using Tcl/Python/Perl.
• Optimize timing, power, performance, and congestion.
• Collaborate with cross-functional teams to achieve design closure.

Must-Have Skills

• 4+ years Physical Design / P&R
• RTL-to-GDSII
• Timing Closure & Constraints Debug
• Advanced-node experience (7nm/5nm/4nm/3nm/2nm)
• Innovus / ICC2 / Fusion Compiler
• Tcl/Python/Perl scripting
• Multi-power domain
• ECO implementation

Preferred

• AI/ML-based EDA automation experience.