Physical Design Engineer (PD)- Pan India

Nanodroits Technologies; Bengaluru; On-site; INR 900,000 - 1,200,000; Full time

Job summary

Nanodroits Technologies in Bengaluru and Pan India seeks a skilled Physical Design Engineer with 3+ years of ASIC/SoC experience to lead block- and chip-level implementation from synthesis to GDSII tape-out.

You will manage floorplanning, CTS, routing, STA across multiple PVT corners, and drive ECOs and physical verification with Cadence Innovus, Synopsys ICC2/Fusion Compiler, and Calibre. Strong scripting skills required.

Qualifications

• 3+ years of hands-on experience in ASIC/SoC physical design.
• Bachelors or Masters in Electrical/Electronics/Computer Engineering or related field.
• Proficient in Cadence Innovus and Synopsys ICC2/Fusion Compiler; Calibre for physical verification.
• Experience with FinFET process nodes and RC extraction, STA concepts, UPF/CPF low-power design.

Responsibilities

• Netlist-to-GDSII ownership: drive complete physical design flow for blocks and subsystems.
• Floor planning and power design: develop block floorplans, macro placement, PDN design.
• Placement and routing: timing-driven placement, CTS, and signal routing with standard EDA tools.
• Timing and signal integrity closure: perform STA to fix setup/hold/crosstalk across PVT corners.
• ECOs: implement pre-layout and post-layout ECOs to meet deadlines.
• Physical verification: run DRC, LVS, and Antenna checks for clean tape-out.
• Power & integrity analysis: static and dynamic IR drop, EM checks, fixes.

Skills

Netlist-to-GDSII ownership

Timing-driven design

Power integrity & PDN design

Scripting (Tcl/Perl/Python)

Education

Electrical Engineering

Electronics Engineering

Computer Engineering

Tools

Cadence Innovus

Synopsys ICC2/Fusion Compiler

Calibre

Tcl

Perl

Python

Job description

We are seeking a skilled and detail-oriented Physical Design Engineer with 3+ years of experience to join our semiconductor implementation team. In this role, you will be responsible for the block-level and chip-level physical design of complex, high-performance integrated circuits. You will own the implementation process from synthesis/netlist handover through to GDSII tape‑out, ensuring strict timing, power, and area (PPA) goals are met.

Location: Bengaluru and Pan India.

Role & responsibilities

• Netlist-to-GDSII Ownership: Drive the complete physical design flow for complex blocks and subsystems.
• Floor planning & Power Design: Develop efficient block floorplans, manage macro placement, and design robust Power Distribution Networks (PDN).
• Placement & Routing: Execute timing-driven placement, Clock Tree Synthesis (CTS), and signal routing using industry-standard EDA tools.
• Timing & Signal Integrity Closure: Perform static timing analysis (STA) to identify and fix setup, hold, and crosstalk violations across various PVT corners.
• Engineering Change Orders (ECO): Implement pre-layout and post‑layout functional and timing ECOs to meet project deadlines.
• Physical Verification: Run and debug Design Rule Checking (DRC), Layout Versus Schematic (LVS), and Antenna checks to ensure a clean tape‑out.
• Power & Integrity Analysis: Perform static and dynamic IR drop analysis, electromigration (EM) checks, and implement fixes.
• Flow Automation: Write and maintain Tcl, Perl, or Python scripts to automate design steps and improve turnaround time.

Preferred candidate profile

• Experience: Minimum 3+ years of hands‑on industry experience in ASIC/SoC physical design.
• Education: Bachelors or Masters degree in Electrical Engineering, Electronics, Computer Engineering, or a related field.
• EDA Tools: Strong proficiency in Cadence Innovus or Synopsys ICC2/Fusion Compiler, along with Calibre for physical verification.
• Technology Nodes: Proven experience working on advanced FinFET process nodes.
• Technical Skills: Deep understanding of constraints generation, STA concepts, UPF/CPF low‑power design, and RC extraction.

Soft Skills: Excellent debugging capabilities, strong teamwork, and clear communication skills to collaborate with RTL and DFT teams.