Physical Design Functional Lead

Cyient Semiconductors; Bengaluru; On-site; INR 2,000,000 - 3,000,000; Full time

Job summary

Cyient Semiconductors is seeking an experienced Physical Design Lead in Bengaluru or Hyderabad to manage all PD projects. The ideal candidate will possess over 15 years of expertise in Physical Design for complex ASICs/SoCs, demonstrating proficiency with EDA tools and leading multi-site teams.

This role encompasses overseeing PD activities, ensuring timely project execution, and mentoring teams to enhance design quality and performance.

Qualifications

• 15+ years of hands-on experience in Physical Design for complex ASICs/SoCs.
• Strong expertise in floorplanning, PnR, clock tree synthesis, STA, timing closure, and sign-off methodologies.
• Solid understanding of advanced technology nodes (7nm/5nm/3nm preferred).

Responsibilities

• Lead and manage all Physical Design (PD) projects across multiple teams and sites.
• Drive chip-level and block-level sign-off for timing, power, IR drop, EM, and DRC/LVS.
• Mentor and guide large teams, providing technical direction and best practices.

Skills

Physical Design

Leadership

Problem-solving

Communication

Tools

Synopsys ICC2

Fusion Compiler

Cadence Innovus

PrimeTime

Voltus/RedHawk

Job description

Physical Design Lead | Experience: 15+ years | Location: Bangalore or Hyderabad

We are seeking an experienced Physical Design Lead to oversee and drive all PD projects across Cyient Semiconductors. The ideal candidate will have a strong track record of managing large teams, delivering complex chips to tape‑out, and guiding all stages of the physical design flow. This role requires deep technical expertise, strong leadership, and the ability to ensure high‑quality, on‑time project execution.

Key Responsibilities

• Lead and manage all Physical Design (PD) projects across multiple teams and sites.
• Oversee end-to-end PD activities including floorplanning, power planning, clock tree synthesis, place-and-route, and timing closure.
• Drive chip-level and block-level sign-off for timing, power, IR drop, EM, and DRC/LVS.
• Collaborate closely with RTL, Architecture, Verification, and Packaging teams for seamless integration.
• Review project schedules, allocate resources, and ensure delivery within timelines and quality targets.
• Mentor and guide large teams, providing technical direction and best practices.
• Resolve complex design challenges and optimize for PPA (Power, Performance, Area).

Required Skills & Qualifications

• 15+ years of hands‑on experience in Physical Design for complex ASICs/SoCs.
• Strong expertise in floorplanning, PnR, clock tree synthesis, STA, timing closure, and sign‑off methodologies.
• Solid understanding of advanced technology nodes (7nm/5nm/3nm preferred).
• Proficiency with EDA tools such as Synopsys ICC2, Fusion Compiler, Cadence Innovus, PrimeTime, and Voltus/RedHawk.
• Experience managing and mentoring large PD teams and leading multi‑site execution.
• Strong analytical, problem‑solving, and debugging skills.
• Excellent communication, stakeholder management, and leadership capabilities.