Physical Design Director

Mulya Technologies; Hyderabad; On-site; INR 3,000,000 - 6,000,000; Full time

Job summary

Mulya Technologies in Hyderabad seeks a senior Physical Design leader to build and grow a high-performing PD team, driving physical implementation of complex ASICs from floor planning to GDSII.

The ideal candidate has deep hands-on PD expertise at advanced nodes, a proven tapeout track record, and the ability to scale a global PD organization while collaborating with RTL, DV, DFT, and packaging teams to ensure first-pass silicon success.

Qualifications

• Deep hands-on expertise in full-chip physical design at advanced nodes.
• Proven track record of successful tapeouts.
• Leadership to scale a Physical Design team and deliver results.
• Collaboration with global PD, RTL, DV, DFT, and packaging teams.

Responsibilities

• Own end-to-end physical implementation of complex SoCs/ASICs from floor planning through GDSII.
• Drive floor planning, CTS, routing, timing closure, power analysis, and physical verification (LVS/RC).
• Lead timing closure across multiple corners and modes (MMMC).
• Oversee power integrity and reliability analysis (IR drop/EM) for manufacturability.
• Manage tapeout schedules, milestones, and cross-functional dependencies.

Skills

Leadership

Team building

Physical Design

Tapeouts

CAD flows

Tools

Cadence Innovus

Synopsys Fusion Compiler

PrimeTime

Calibre

RedHawk/Voltus

StarRC

Job description

Top30 Semiconductor Organization in the world

Role Overview

We are seeking a Physical Design Director to lead and grow our Physical Design function in Hyderabad. This is a senior leadership role responsible for building and managing a high-performing PD team, driving physical implementation of complex, high-speed connectivity ASICs, and establishing best-in-class design methodology and flows.

The ideal candidate brings deep hands-on expertise in full-chip physical design at advanced nodes, a proven track record of successful tapeouts, and the leadership ability to scale a team and deliver results in a fast-paced, high-growth environment. This role will work closely with global PD, RTL, DV, DFT, and packaging teams to ensure first-pass silicon success.

Key Responsibilities

Leadership & Team Buiding

• Build, lead, and mentor a high-performing Physical Design team in Hyderabad across PnR, STA, EMIR/Power Integrity, and CAD/methodology fun


• ctionsDefine team structure, hiring roadmap, and career development paths for PD eng


• ineersFoster a culture of technical excellence, ownership, and continuous impro


• vementPartner with global PD leadership (US and Israel sites) to align on strategy, methodology, and execution priorities


• Physical Design Execution


• Own end-to-end physical implementation of complex SoCs/ASICs from floor planning through GDSII


• signoffDrive floor planning, placement, clock tree synthesis (CTS), routing, timing closure, power analysis (IR drop/EM), and physical verification (D


• RC/LVS)Lead timing closure across multiple corners and modes (MMMC), ensuring robust STA signoff at advanced nodes (5nm and


• below)Oversee power integrity and reliability analysis (IR drop, EM) to meet design quality and manufacturability


• targetsManage tapeout schedules,milestones, and cross-functional dependencies to deliver on time and within PPAtargetsMethodology & CAD


• Establish and continuously improve PD flows, methodologies, checklists, and best practices for first-pass


• successEvaluate and deploy EDA tools (Cadence Innovus, Synopsys Fusion Compiler, PrimeTime, Calibre, RedHawk/Voltus, StarRC, etc.)Drive automation and scripting (Tcl, Python, Perl) to improve turnaround time and design