Principal Physical Design Engineer

Mulya Consulting; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Mulya Consulting in Bengaluru is seeking a Principal Physical Design Engineer (RTL-to-GDSII) to own the full flow for large blocks and SoCs using Cadence Digital Suite. You will drive high-speed design from synthesis to sign-off, focusing on PPA and reliability.

The role demands 14–20 years of PD experience on sub-5nm nodes, deep knowledge of EUV, multi-patterning, STA, PV, PI, and ECOs, plus Tcl/Python scripting to automate flows.

Qualifications

• 14–20 years of Physical Design experience with multiple sub-5nm tape-outs.
• Expertise in STA, PV and PI methodologies and ECO flow.
• Strong Tcl and Python scripting for custom flows and data mining.
• Experience leading full-flow SoC projects from Synthesis to Sign-off.

Responsibilities

• Full-Flow Ownership: drive Synthesis through Sign-off for large blocks/SoCs using Cadence Digital Suite.
• PPA Optimization: optimize interaction of library cells, metal stacks and tool engines.
• Develop scalable, automated methodologies to reduce manual iterations.
• Collaborate with RTL, Architecture and DFT to influence early design decisions.
• Identify bottlenecks and architect automation to bypass them.

Skills

Sub-5nm flow

PPA optimization

RTL-to-GDSII experience

Scripting Tcl/Python

Mentorship

Tools

Cadence Innovus

Tempus

Joules

Pegasus

Voltus

Job description

Principal Physical Design Engineer (RTL-to-GDSII)

Bangalore (Hybrid - 2 days office, 3 days home)

Experience: 14-20 Years

Technology Focus: Sub-5nm (3nm/2nm)

The Vision

We are seeking a Principal Physical Design Engineer who thrives on complexity and rejects the black box approach to EDA tools. This role is for a First Principles thinker who questions the status quo. If a standard flow isn't yielding the desired PPA (Power, Performance, Area), you dive into the PDK, the tool algorithms, and the methodology to find a better way. You are responsible for transforming raw RTL into world-class silicon by eliminating systemic bottlenecks and building a scalable, predictable path to GDSII.

Key Responsibilities

• Full-Flow Ownership: Lead the implementation of massive, high-speed blocks/SoCs from Synthesis through Sign-off using the Cadence Digital Suite.
• PPA Optimization: Push the theoretical limits of the PDK and tools. You will analyze and optimize the interplay between library cells, metal stacks, and tool engines to squeeze out every millivolt and picosecond.
• Methodology & Scalability: Build and refine a Push-Button style execution methodology that is robust, repeatable, and minimizes manual human-in-the-loop iterations.
• Cross-Functional Left-Shift: Collaborate with RTL, Architecture, and DFT teams to influence design decisions early. You will drive a holistic approach where physical constraints inform the architecture, not just react to it.
• Bottleneck Elimination: Identify drag in the execution pipeline—whether it’s runtime, convergence issues, or tool limitations—and architect automated solutions to bypass them.

Technical Qualifications

• Experience: 14-20 years in Physical Design with a proven track record of multiple sub-5nm tape-outs.
• Tool Suite: Mastery of Cadence Innovus, Tempus, Joules, Pegasus, and Voltus.
• Advanced Nodes: Deep understanding of sub-5nm physics: EUV constraints, multi-patterning, FinFET and IR/EM challenges.
• Sign-off: Expert-level knowledge in Static Timing Analysis (STA), Physical Verification (PV), and Power Integrity (PI) and ECO methodology.
• Scripting: Proficiency in Tcl and Python to develop custom flow wrappers and data-mining tools for PPA analysis.

Soft Skills & Leadership

• Holistic Thinking: You look at the Big Picture. You solve timing by fixing the floorplan or the RTL/ARCH.
• Influence & Rapport: You can build strong technical bridges with Front-End, Foundry, and EDA vendors to align on a unified execution strategy.
• Critical Thinking: You operate on first principles. You don't just follow a vendor's Best Practices if they don't make sense for our specific architecture.
• Mentorship: You act as a force multiplier, elevating the technical competence of the entire PD team.

Why Join This Team?

In this role, you aren't just a user of tools; you are an engineer who shapes how silicon is built. You will have the autonomy to overhaul legacy flows and the resources to execute on cutting-edge nodes that define the industry's future.