Physical Design Lead - Semiconductor Chip Design

Larsen & Toubro Ltd; Bengaluru; On-site; INR 1,800,000 - 3,600,000; Full time

Job summary

LTSCT — L&T Semiconductor Technologies Limited in Bangalore, India, seeks a Physical Design Lead with 10+ years of hands-on PD experience to drive the architecture-to-silicon loop for multi-chiplet systems. You will steer floorplanning, P&R, VP, timing closure, and signoff for 2nm-class designs, collaborating across front-end and backend teams.

This leadership role requires mentoring backend PD engineers, defining PD methodology, and ensuring tapeout readiness with robust QoR, power integrity,

Qualifications

• 10+ years of hands-on physical design with a large taped-out chiplet at advanced nodes.
• Deep knowledge of floorplanning, P&R, and timing closure for GHz-class designs.
• Experience with PD flows and tools and signoff for tapeout.

Responsibilities

• Own full-chip and block-level floorplanning strategy for ~800mm² 2nm compute chiplets.
• Drive place-and-route, clock tree synthesis, and congestion optimization to meet 2 GHz.
• Lead STA analysis and timing closure across corners and PVT conditions.
• Own PD signoff — DRC, LVS, antenna, ERC, and foundry handoff for tapeout.
• Manage power integrity and thermal-aware placement for high-density PE arrays.
• Coordinate chiplet-level PD with UCIe PHY placement and interposer constraints.
• Define PD methodology and mentor backend PD teams; track schedule and risks.

Skills

Floorplanning

P&R

Timing closure

Physical verification

Chiplet design

Scripting (Tcl/Python)

Education

M.Tech/MS in EE/ECE or equivalent

Tools

Fusion Compiler

ICC2

Innovus

PrimeTime

Calibre

PVS

StarRC

Job description

Physical Design (PD) Lead

Location: Bangalore, India | Company: LTSCT — L&T Semiconductor Technologies Limited Reporting To: Chandra — Senior Architect, DC HW Systems | Experience: 10+ years (mandatory)

Role Summary

The Physical Design Lead owns the loop from architecture to silicon realization for the full xPU SiP. You will drive floorplanning, place-and-route, physical verification, timing closure, and signoff across ~800mm² chiplets on TSMC 2nm, acting as the primary bridge between the front-end architecture team and the backend PD organization. This is a hands‑on leadership role accountable for delivering manufacturable, timing‑clean, power‑efficient physical databases for tapeout.

Key Responsibilities

Own full-chip and block-level floorplanning strategy for ~800mm² 2nm compute chiplets, including power grid planning, macro placement, and partitioning of dual BFOS arrays, SRAM banks, and NoC planes.

Drive place-and-route, clock tree synthesis, and congestion/utilization optimization to meet 2 GHz operating frequency targets.

Lead static timing analysis and timing closure across all corners, modes, and PVT conditions, resolving setup/hold, cross‑talk, and signal‑integrity violations.

Own physical verification signoff — DRC, LVS, antenna, ERC, and DFM — and drive clean handoff to the foundry for tapeout.

Manage power integrity (IR-drop, EM) and thermal‑aware placement for high‑density PE arrays operating at datacentre power envelopes.

Coordinate chiplet‑level physical partitioning with UCIe PHY placement and interposer/advanced‑packaging constraints.

Define and enforce PD methodology, flows, and QoR metrics; mentor the backend PD team and interface daily with architecture, DFT, and packaging teams.

Track schedule, resources, and tapeout readiness, escalating risks and driving cross‑functional closure.

Required Skills & Experience

• 10+ years of hands‑on physical design experience with at least one large SoC/chiplet taped out at an advanced node (7nm/5nm/3nm; 2nm exposure strongly preferred).
• Deep expertise in floorplanning, P&R, and timing closure for multi-million-instance, GHz-class designs.
• Mastery of industry PD flows and tools (Synopsys Fusion Compiler/ICC2, Cadence Innovus, PrimeTime, StarRC, Calibre/PVS).
• Strong command of STA concepts — multi-corner multi-mode, OCV/AOCV/POCV, CPPR, and constraint (SDC) development.
• Hands‑on experience with physical verification signoff (DRC/LVS/antenna) and foundry tapeout handoff.
• Solid understanding of power integrity (IR/EM), low‑power design (UPF/CPF, multi-voltage, power gating), and clock architecture.
• Experience with advanced‑packaging and chiplet flows (2.5D/3D, interposers, UCIe PHY integration) is a strong plus.
• Proficiency in Tcl/Python scripting for flow automation and QoR analysis.
• Proven ability to lead and mentor backend teams and to bridge architecture-to-implementation.
• Excellent problem‑solving, communication, and cross‑functional collaboration skills.

Preferred Qualifications

• Experience taping out AI accelerator, HPC, or datacentre-class silicon.
• Exposure to TSMC 2nm (N2) design rules and PDK.
• Familiarity with HBM controller/PHY physical integration.
• M.Tech/MS in EE/ECE or equivalent.