Senior Principal Physical Design Engineers

Kandou AI; Bengaluru; On-site; INR 3,500,000 - 6,000,000; Full time

Job summary

Kandou AI in Bengaluru (Hybrid/In-house) seeks Senior Principal Physical Design Engineers to lead digital PD for cutting-edge chiplet-based AI memory fabrics. You will collaborate with Architecture, RTL and DFT teams to drive high-quality silicon and tight timing closures.

Ideal candidates bring 15–25 years in semis, deep PD expertise, strong scripting, and a proven track record in hierarchical floorplanning, tape-outs, and cross-project reuse.

Qualifications

• 15-25 years’ experience in the semiconductor industry, with min. 5 years in a digital Physical Design technical leadership role
• Experience on 28nm, 14/16nm, 7nm processes
• Proficient with Cadence Genus/Innovus and verification tools including LEC, Calibre/PVS DRC/LVS
• Expertise in Timing Constraints and STA
• Exposure to CPF/UPF flows is highly desirable
• Experience in hierarchical floor planning and tape-out procedures
• Experience in library setup and flow development for cross-project reuse
• Experience in DFT methodologies and implementation schemes (Required)

Responsibilities

• Work with Architecture, RTL, DFT to ensure first-time-right silicon production
• Improve timing constraints and perform static timing analysis and sign-off
• Synthesize, floor-plan, power grid design, place & route, clock tree synthesis, IR-drop analysis
• Develop scripts/methodologies/flows and improve PD processes
• Provide design views for LIB/LEF/DEF/GDS/SPEF in digital PD flows
• Support IP and chip-level integration and customer collaboration
• Manage workload and schedule, report to management

Skills

Leadership in PD

Timing constraints

RTL to GDS flow

Scripting (Shell/TCL/Python)

Data management

Team communication

Education

Bachelor/Master in ECE/CS

Tools

Cadence Genus

Cadence Innovus

Calibre DRC/LVS

Parasitics extraction

DFT tools

Job description

Senior Principal Physical Design Engineers

https://www.thecube.net/events/nyse/ai-factory-data-center-of-the-future/content/Videos/d1ad8af3-1424-4336-a9b3-1d02b5a354b4

we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable adoption.

Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency — unlocking unprecedented efficiency for AI training and inference at scale.

our architecture is not just an incremental improvement — it’s a foundational shift in how AI hardware is built for the future.

Physical Design Engineers based in Hyderabad OR Bangalore

Required competences - Experience

• 15-25 years’ experience in the semiconductor industry, with min. 5 years in a digital Physical Design technical leadership role
• Experience on modern semiconductor process technologies including 28nm, 14/16nm, 7nm
• Experienced user of EDA tools for design and verification such as, Cadence Genus and Innovus, LEC, Calibre/PVS DRC/LVS, parasitics extraction, EM and IR drop, ESD, etc.
• Expertise in Timing Constraints and Static Timing Analysis (STA)
• Experience in CPF/UPF technologies and flows is highly desirable
• Exposure to flip-chip package technologies and wire bond package technologies
• Experience in hierarchical floor planning and implementation
• Experience in release management and tape out procedures
• Experience in library setup and flow development with focus on cross project reusability
• Experience in DFT methodologies and implementation schemesRequired

Required competences - Skills

• Good understanding of RTL to GDS implementation flow (synthesis, P&R, LEC, PV)
• Self-motivated, with strong sense of ownership and responsibility. Good communicator and team player
• Good scripting capabilities (shell, TCL, Python, make) and good understanding of data management (revision control system)

Responsibility and Authority

• As a Physical Design Engineer, you will work closely with the Architecture, RTL, DFT teams to ensure first-time-right high-volume silicon production
• Timing constraints improvement and timing constraints validation, signoff Static Timing Analysis and block-level timing closure
• Synthesis, block level floor-planning, power grid design, place & route, clock tree synthesis, electromigration / IR-Drop analysis, power/signal integrity analysis, crosstalk analysis, formal equivalence checking and physical verification (DRC / LVS / Antenna)
• Participate in developing improvements to scripts/methodologies/flows
• Interact closely with the design team to understand requirements and implement solutions as also helping on providing design views for use with digital PD flows (LIB, LEF, DEF, GDS, SPEF, etc.)
• Support IP and chip level integration
• Support and interact with customers on requirements and IP delivery
• Manage workload and schedule and report to internal management team

Education

• Bachelors/Masters of Engineering in Electronics and Electrical Engineering/Computer Science (equivalent or higher)