Physical Design (PD) Solution Architect

Vrinda International; Bengaluru; On-site; INR 4,050,000 - 4,950,000; Full time

Job summary

Vrinda International is seeking an experienced Physical Design (PD) Solution Architect to lead the physical implementation strategy for complex SoCs. You will serve as the technical authority on architecture feasibility and project delivery across global teams.

The role requires deep expertise in floorplanning, CTS, timing closure, and power optimization, with hands-on use of Synopsys ICC2, Fusion Compiler, and Cadence Innovus.

Qualifications

• Experience in Physical Design.
• Multiple successful tape-outs on advanced technology nodes (10nm and below).
• Strong expertise in Floorplanning, CTS, Timing Closure, Power Optimization.

Responsibilities

• Lead physical design architecture and strategy for complex SoCs.
• Define methodology and ensure successful project delivery.
• Optimize Power, Performance, and Area (PPA) across global teams.

Skills

Physical Design

Tape-outs

Floorplanning

CTS

Timing Closure

Power Optimization

SoCs >100M gates

Signoff methodologies

TSMC nodes

Tools

Synopsys ICC2

Fusion Compiler

Cadence Innovus

UPF & multi-voltage designs

AI-based EDA tools (DSO/Cerberus)

Job description

Job Description

We're Hiring | Physical Design (PD) Solution Architect

Experience:9+ Years

CTC: Up to ₹45LPA (Based on Experience)

Employment Type: Full-Time

Experience & CTC

Level

Experience

CTC

C2
9–12 Years
₹35 LPA

D1
12–14 Years
₹41 LPA

D2
14+ Years
₹45 LPA

Job Summary

We are looking for an experienced Physical Design (PD) Solution Architect to lead physical implementation strategy, methodology definition, PPA optimization, and implementation planning for complex SoCs. The ideal candidate will serve as the technical authority for physical design architecture, feasibility analysis, and successful project delivery across global teams.

Requirements

Mandatory Skills

experience in Physical Design.

• Multiple successful tape‑outs on advanced technology nodes (10nm and below).
  

Strong expertise in:

• Floorplanning
  
• CTS (Clock Tree Synthesis)
  
• Timing Closure
  
• Power Optimization
  

Hands‑on experience with:

• Synopsys ICC2
  
• Fusion Compiler
  
• Cadence Innovus
  
• Experience with UPF and multi-voltage designs.
  
• Experience working on large SoCs (>100M gates).
  
• Strong understanding of signoff methodologies.
  
• Mandatory experience with TSMC technology nodes.
  
• Experience with AI-based EDA tools such as DSO or Cerberus.