MTS Verification Engineering

Rambus.com; Bengaluru; On-site; INR 700,000 - 1,000,000; Full time

Benefits offered by this job

Flexible work environment

Hybrid work model

Job summary

Rambus.com is seeking an experienced Design Verification Engineer for its SoftIP Products team in Bengaluru, India. In this full-time position, the successful candidate will engage in pre-silicon RTL verification related to PCIe-Express technologies.

The role offers a hybrid work environment, with an expectation of three days onsite each week. Responsibilities include testbench development, functional coverage planning, and regression test management.

Qualifications include a Bachelor's degree in EE/CS and experience with SystemVerilog and UVM testbenches.

Qualifications

• 3-5 years relevant work experience in HDL logic Design-Verification.
• Familiarity with PCI-Express protocol is highly desirable.
• Project experience related to RTL verification.

Responsibilities

• Develop testbench and test sequences for new controller technologies.
• Plan functional coverage and code coverage items.
• Develop and monitor regression tests, debug/triage test environments.
• Support verification environment scripting and capabilities.

Skills

SystemVerilog

UVM testbench

Python

TCL scripting languages

Education

Bachelor's Degree in EE/CS

Job description

Overview

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional experienced Design Verification Engineer to join our SoftIP Products development team in Bangaluru, India. The successful candidate will participate in pre-silicon RTL Verification activities related to development and product-delivery of PCIe-Express related technologies. This is a Full Time position, reporting to the local onsite technical management.

Rambus offers a flexible work environment, embracing a hybrid approach for the majority of our office-based roles. We encourage employees to spend an average of at least three days per week working onsite while also allowing for two days of remote work.

Responsibilities

Duties in this position will include:

• Testbench and test sequence development for verification of new controller technologies and features
• Functional coverage planning, coverage item coding, and test suite augmentation to achieve Functional Coverage
• Regression test development, monitoring, debug/triage, and correction to test environment, sequences, debug of controller RTL design
• Development & support of Verification environment scripting and capabilities

Qualifications

• Bachelors Degree or above in EE/CS, project experience related to HDL logic Design-Verification, with 3-5 years relevant work experience.
• SystemVerilog and/or UVM testbench, Verilog/SystemVerilog logic desig, /RTL familiarity/project work
• Pre-existing Experience / familiarity with PCI-Express protocol is highly desireable
• Working experience with Python and TCL scripting languages preferred