PCIe Design Verification Engineer

Lookup It Solutions; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Lookup It Solutions in Bengaluru is seeking a seasoned Verification Engineer to develop and maintain UVM-based environments using SystemVerilog. You will create testbenches, sequences, and coverage models to verify PCIe across Gen3-Gen6, and debug TL, DLLP, LTSSM issues.

The role requires strong SystemVerilog/UVM, PCIe protocol knowledge, and scripting skills in Python and Shell. You will collaborate with design and architecture teams to enhance verification infrastructure and product

Qualifications

• Strong hands-on experience in SystemVerilog and UVM.
• Good understanding of PCIe Gen3/Gen4/Gen5/Gen6 protocols.
• Experience with PCIe Transaction Layer (TLP), Data Link Layer (DLLP), and LTSSM.
• Proficiency in Verdi, VCS, Linux and version control tools such as Perforce.
• Good programming and scripting skills in Python and Shell scripting.
• Understanding of OOP concepts and RTL verification.
• Strong problem-solving and analytical skills.

Responsibilities

• Develop and maintain UVM-based verification environments using SystemVerilog.
• Create and execute testbenches, virtual sequences, test scenarios, and functional coverage models.
• Perform PCIe protocol verification across Gen3, Gen4, Gen5, and Gen6.
• Verify PCIe Transaction Layer (TLP), Data Link Layer (DLLP), LTSSM, and protocol state transitions.
• Implement error injection scenarios and identify coverage gaps in verification environments.
• Debug complex RTL, BFM, LTSSM, and TLP failures using Verdi, VCS, and other debugging tools.
• Perform root-cause analysis and support functional and coverage closure.
• Develop Python and Shell scripts to automate verification, testing, and reporting workflows.
• Work closely with design, architecture, and verification teams to resolve issues.
• Contribute to improving verification infrastructure, test quality, and overall product reliability.

Skills

SystemVerilog

UVM

PCIe protocols

Testbench development

Python

Shell scripting

Verdi

VCS

Perforce

OOP/RTL verification

Troubleshooting

Tools

Verdi

VCS

Perforce

Job description

Key Responsibilities

• Develop and maintain UVM-based verification environments using SystemVerilog.
• Create and execute testbenches, virtual sequences, test scenarios, and functional coverage models.
• Perform PCIe protocol verification across Gen3, Gen4, Gen5, and Gen6.
• Verify PCIe Transaction Layer (TLP), Data Link Layer (DLLP), LTSSM, and protocol state transitions.
• Implement error injection scenarios and identify coverage gaps in verification environments.
• Debug complex RTL, BFM, LTSSM, and TLP failures using Verdi, VCS, and other debugging tools.
• Perform root-cause analysis and support functional and coverage closure.
• Develop Python and Shell scripts to automate verification, testing, and reporting workflows.
• Work closely with design, architecture, and verification teams to resolve issues.
• Contribute to improving verification infrastructure, test quality, and overall product reliability.

Required Skills

• Strong hands‑on experience in SystemVerilog and UVM.
• Good understanding of PCIe Gen3/Gen4/Gen5/Gen6 protocols.
• Experience with PCIe Transaction Layer (TLP), Data Link Layer (DLLP), and LTSSM.
• Knowledge of verification methodologies, testbench development, and functional coverage.
• Experience in error injection, protocol validation, and debugging.
• Proficiency in Verdi, VCS, Linux, and version control tools such as Perforce.
• Good programming and scripting skills in Python and Shell scripting.
• Understanding of OOP concepts and RTL verification.
• Strong problem‑solving and analytical skills.

Preferred Skills

• Experience with PCIe BFM development and integration.
• Knowledge of AER, Configuration Space, Equalization, Ordered Sets, and Credit‑Based Flow Control.
• Experience in PCIe error reporting and logging infrastructure.
• Familiarity with AXI‑Stream, DMA controllers, FSM design, and synthesizable SystemVerilog.
• Experience with PCIe power management features, including L0p sub‑state.
• Knowledge of C/C++ programming and transaction‑level modeling.
• Experience with semiconductor, VLSI, SoC, or high‑speed interconnect verification projects.