Design Engineer – Verification (BB812FT RM 4421)

Source-Right; Dadri; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Source-Right is seeking a Design Engineer – Verification to drive functional and performance verification across SOC/Subsystem/SoC levels. You will map requirements into a traceable verification plan and collaborate with SoC/IP teams to improve productivity with a zero-defect mindset.

You will develop verification test benches, components, and test cases for simulation, formal verification and emulation, while debugging failures and contributing to coverage and assertion strategies.

Qualifications

• BTech/MTech with 8–12 years of SOC/IP/Subsystem verification experience.
• Hands-on knowledge of C and UVM/SV based test environments.
• HDLs (Verilog/VHDL) and simulators (Synopsys/Cadence/Mentor) are a MUST.
• Ability to debug RTL/Gate netlists and understand design/architecture.
• Coverage-driven verification for functional and performance requirements.

Responsibilities

• Develop verification test benches and verification components.
• Create test cases for simulation, formal verification and emulation.
• Debug failures, reproduce issues and perform root-cause analysis.
• Implement direct and constrained-random stimulus.
• Develop system Verilog assertions and formal verification approaches.

Skills

Verification planning

UVM VIPs

Constrained-random stimulus

RTL analysis

SystemVerilog assertions

Formal verification

Debugging

Root cause analysis

Education

BTech/MTech in ECE/CS

Tools

Verilog/VHDL

Synopsys Cadence Mentor

Job description

Position: Design Engineer – Verification (BB812FT RM 4421)

The Verification role will involve many aspects of Functional, Performance verification using most effective methodologies in context of Module/Subsystem/SoC /System Level. A strong ability to map requirements into a traceable verification plan is important. The ideal candidate will partner with local and global SoC and IP developers to drive best practices with a target of ongoing productivity improvement. A “zero-defect” mindset is a key enabler. Responsibilities encompass the development of verification test bench, development of verification components, test case development for simulation, formal verification and emulation, debugging failures and creating simulation cases for various studies

• Expectations include:
• Verification planning;
• Verification test bench development and implementation;
• Development of verification test bench components such as drivers, monitors, response checkers as well as use most advanced UVM VIPs;
• Development of direct and constrained-random stimulus;
• Understands and analyzes RTL code, functional, assertion coverage results;
• Understands Develop functional coverage;
• Understands and develops system Verilog assertions;
• Understands and implements formal verification methods;
• Strong skills in debug, failure re-creation and root cause analysis
• Applicant should have efficient debugging and logic skills.

Position: Design Engineer – Verification (BB812FT RM 4421)

Job Summary

The Verification role will involve many aspects of Functional, Performance verification using most effective methodologies in context of Module/Subsystem/SoC /System Level. A strong ability to map requirements into a traceable verification plan is important. The ideal candidate will partner with local and global SoC and IP developers to drive best practices with a target of ongoing productivity improvement. A “zero-defect” mindset is a key enabler. Responsibilities encompass the development of verification test bench, development of verification components, test case development for simulation, formal verification and emulation, debugging failures and creating simulation cases for various studies

• Expectations include:
• Verification planning;
• Verification test bench development and implementation;
• Development of verification test bench components such as drivers, monitors, response checkers as well as use most advanced UVM VIPs;
• Development of direct and constrained-random stimulus;
• Understands and analyzes RTL code, functional, assertion coverage results;
• Understands Develop functional coverage;
• Understands and develops system Verilog assertions;
• Understands and implements formal verification methods;
• Strong skills in debug, failure re-creation and root cause analysis
• Applicant should have efficient debugging and logic skills.

Job Qualifications

• BTech/MTech with 8-12 years’ experience in SOC/IP/Subsystem verification of multimillion Gate complex Design with multiple clocks/power domains. Experience in below areas with strong hands on knowledge in below areas is needed
• C and UVM/SV based Test environment,
• HDLs (Verilog/VHDL), simulators (Synopsys/Cadence/Mentor) is a MUST
• Understanding of the design/architecture and ability to debug RTL/Gate netlist is MUST
• Coverage driven Verification for addressing Functional, Performance requirement of the SoC, regression management
• Microcontroller architecture, ARM Cores, Interconnect(NIC, FlexNoC), Cache Coherency,
• Bus Protocols like AHB/AMBA,AXI, ACE

Following Skills Will Have Additional Value

• Memory controllers (Flash, SRAM,DDR3/4/LPDDR)
• Protocols like PCIe, MIPI, GPU (Graphics processing), VPU (Video Processing), Ethernet, USB, Image
• Formal verification methodologies and Apps, AVIP, PinMuxing Verification, Randomization
• Low Power intent verification using CPF, UPF
• Exposure to pre silicon validation/emulation (Palladium, Zebu)/FPGA Prototyping would be a plus