PCIe Verification BB510FT RM 4464

Source-Right; Hyderabad; On-site; INR 2,500,000 - 4,200,000; Full time

Job summary

Source-Right in Hyderabad seeks a PCIe Verification engineer with expert-level experience in PCIe IP/sub-systems and UVM-based verification. The role requires defining test plans for blocks, sub-systems, and SOCs, and delivering robust test benches while maintaining high-quality verification flows.

The candidate should have 5–10 years of NAND, DDR and PCIe verification, strong ASIC simulation expertise, and superior debugging skills to support complex SoC projects.

Qualifications

• 5-10 years of relevant experience in NAND, DDR and PCIe verification.
• Expertise with ASIC simulation tools and advanced verification methods.
• Expert in verification languages (UVM, SystemVerilog) and writing block-level/SoC test plans.

Responsibilities

• Define block, sub-system and SOC top level test plans.
• Develop UVM-based SV test benches for PCIe IP/sub-systems.
• Apply verification methodologies, flows and quality metrics to projects.
• Demonstrate strong debugging and problem-solving skills within the team.

Skills

IP/Block/Subsystem Verification

SV/UVM Verification

Interfaces AXI/AHB

PCIE Protocols

Perl/Python Scripting

Education

B.S. in electrical engineering, computer science

Job description

Position: PCIe Verification (BB510FT RM 4464)

Education: B.S. in electrical engineering, computer science with extensive industry experience.

Candidates must be comfortable with the Hyderabad location.

Job Requirements

• An expert level experience with PCIe IP/sub-systems.
• Highly experienced with defining block, sub-system and SOC top level test plans.
• An expert level with developing UVM-based SV test-benches.
• Deep understanding and knowledge of verification methodologies flows and quality metrics.
• Great debugging and problem-solving skills.
• Team player with great interpersonal communication skills.

Job Qualifications

• At least 5-10 years of relevant experience in Nand, DDR and PCIe verification.
• Strong and relevant expertise with ASIC simulation tools and advanced verification methods.
• Expert level in verification languages such as UVM and System Verilog.Relevant experience with writing block-level and SoC test-plans.

  Skills Required

  • IP/Block/Subsystem Verification (RTL Front end verification) – minimum 5 years
  • SV, UVM Verification – minimum 4 Years
  • Interfaces (AXI/AHB) – minimum 2 years
  • Protocols (PCIE) – minimum 2 years
  • Scripting (Perl/Python) – Optional.

  Requirements: