Lead MTS Verification Engineering

Rambus.com; Bengaluru; On-site; INR 1,600,000 - 2,200,000; Full time

Job summary

Rambus.com is looking for a Senior/Lead Design Verification Engineer to join its Memory Controller IP team in Bangalore, India. The role involves pre-silicon RTL verification activities related to various DRAM technologies. The successful candidate will develop testbenches and verification scripts while ensuring thorough functional coverage. Candidates must have a Bachelor's degree in EE/CS and a minimum of 5 years of experience in HDL logic design verification. Rambus offers a flexible hybrid work environment, allowing for both onsite and remote working days.

Qualifications

• Minimum 5 years experience with HDL logic Design-Verification.
• Pre-existing experience with DDR DRAM technology preferred.

Responsibilities

• Develop testbench and test sequence for new controller technologies.
• Plan functional coverage and augment test suite for coverage.
• Develop regression tests, monitor and debug the test environment.
• Support Verification environment scripting and capabilities.

Skills

System Verilog testbench

HDL logic Design-Verification

Verilog/System Verilog logic design/RTL fluency

Experience with Python

Experience with TCL scripting

Education

Bachelors Degree in EE/CS

Tools

Python

TCL

Job description

Overview

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Senior/Lead Design Verification Engineer to join our Memory Controller IP team in Bangalore, India. The successful candidate will participate in pre-silicon RTL Verification activities related to Memory Controller SoftIP development, on leading-edge DDR, HBM, GDDR, and LPDDR DRAM controller technologies. This is a Full Time position, reporting to a local onsite manager of India Memory Controller Verification.

Rambus offers a flexible work environment, embracing a hybrid approach for the majority of our office-based roles. We encourage employees to spend an average of at least three days per week working onsite while also allowing for two days of remote work.

Responsibilities

Duties in this position will include:

• Testbench and test sequence development for verification of new controller technologies and features
• Functional coverage planning, coverage item coding, and test suite augmentation to achieve Functional Coverage
• Regression test development, monitoring, debug/triage, and correction to test environment, sequences, debug of controller RTL design
• Development & support of Verification environment scripting and capabilities

Qualifications

Bachelors Degree or above in EE/CS, minimum 5 years experience with HDL logic Design-Verification

• System Verilog testbench, Verilog/System Verilog logic design/RTL fluency a must
• Pre-existing Experience / familiarity with DDR DRAM technology a strong preference
• Working experience with Python and TCL scripting languages preferred