Mixed Signal Verification Engineer

leadIC Design Pvt Ltd; Hyderabad; On-site; INR 180,000 - 280,000; Full time

Benefits offered by this job

Health insurance

Job summary

leadIC Design Pvt Ltd is seeking an experienced Mixed-Signal Verification / AMS Co-Simulation Engineer to verify complex mixed-signal IPs by combining transistor-level analog simulations with digital RTL/behavioral models. You will collaborate with Analog, Digital, Verification, Modeling and Physical Design teams to ensure functional correctness across analog and digital domains.

The role involves building automated verification environments, developing high-level models, and validating them

Qualifications

• Bachelor's or Master's degree in ECE, EEE, VLSI, Microelectronics or related discipline.
• 6–10 years of hands-on experience in mixed-signal verification or AMS verification.
• Strong understanding of mixed-signal simulation methodologies.
• Experience with Cadence AMS Designer and Spectre.

Responsibilities

• Perform block-level and full-chip mixed-signal simulations with analog/SPICE and digital engines.
• Configure and execute mixed-signal simulations using Cadence tools and Xcelium/Spectre.
• Debug analog/digital interfaces, convergence, and simulation failures.
• Develop behavioral models for analog blocks and reusable verification environments.
• Build verification plans, coverage metrics, and regression flows.

Skills

Mixed-signal verification

AMS verification

SystemVerilog/UVM

Analog-digital co-simulation

Python/Tcl/Perl scripting

Cadence AMS Designer

Spectre

UVM-AMS

RNM / wreal

Education

Bachelor's or Master's in ECE/EE/VLSI

Tools

Cadence AMS Designer

Xcelium

Spectre

Job description

We are looking for an experienced Mixed-Signal Verification / AMS Co-Simulation Engineer with strong hands-on expertise in analog-digital co-simulation, behavioral modeling, SystemVerilog/UVM-based verification, and mixed-mode simulation.

The ideal candidate will have experience verifying complex mixed-signal IPs by combining transistor-level analog simulations with digital RTL/behavioral models, developing behavioral models for analog blocks, and building automated verification environments.

You will work closely with Analog Design, Digital Design, Verification, Modeling and Physical Design teams to ensure functional correctness and robust interaction between analog and digital domains.

Key Responsibilities

• Perform block-level and full-chip mixed-signal simulations combining analog/SPICE solvers with digital simulation engines.
• Configure and execute mixed-signal simulations using tools such as Cadence AMS Designer, Xcelium and Spectre.
• Debug analog/digital interface behavior, connectivity issues, convergence problems and simulation failures.
• Configure mixed-mode environments where selected blocks are simulated at transistor/schematic level while other blocks use behavioral models.
• Develop high-level behavioral models for analog and mixed-signal blocks using:
  • SystemVerilog RNM / wreal
• Develop models that accurately represent functional and electrical behavior required for digital/mixed-signal verification.
• Validate behavioral models against transistor-level schematics and simulation results.
• Optimize models for simulation accuracy, performance and convergence.
• Develop reusable, metric-driven verification environments using SystemVerilog and UVM.
• Build verification environments suitable for mixed-signal / UVM-AMS simulations.
• Develop test scenarios covering analog/digital interfaces, corner cases and system-level interactions.
• Define verification strategies, test plans and functional coverage metrics.
• Analyze mixed-signal waveforms and identify functional issues across analog and digital domains.
• Debug:
  • Analog/digital interface issues
  • Waveform anomalies
  • Model/schematic mismatches
  • Simulation configuration issues
• Drive functional coverage and verification closure.
• Collaborate with analog and digital designers to identify root causes and implement fixes.
• Develop and execute verification plans to establish functional equivalence between behavioral models and transistor-level schematics.
• Compare behavioral-model outputs against schematic/SPICE simulations across relevant operating conditions.
• Validate model behavior across PVT corners and critical use cases.
• Identify discrepancies and work with model/design owners to resolve them.
• Develop automation scripts using Python, Perl and/or Tcl.
• Automate:
  • Simulation setup
  • Test management
  • Result collection
  • Coverage analysis
• Develop reusable utilities to improve mixed-signal verification productivity.

Required Skills & Qualifications

• Bachelor's or Master's degree in ECE, EEE, VLSI, Microelectronics or related discipline.
• 6–10 years of hands-on experience in mixed-signal verification, AMS verification or analog/digital co-simulation.
• Strong understanding of mixed-signal simulation methodologies.
• Hands‑on experience with one or more of:
  • Cadence AMS Designer
  • Spectre
• Strong programming/verification experience with:
  • UVM
  • SystemVerilog RNM / wreal
• Experience developing analog behavioral models and validating them against transistor-level implementations.
• Strong understanding of analog/digital interfaces and mixed-signal verification challenges.
• Good debugging and waveform‑analysis skills.
• Experience developing automated verification/regression flows using Python, Tcl or Perl.

Domain Expertise

Experience verifying one or more of the following analog/mixed-signal blocks is highly desirable:

• DLL – Delay Locked Loop
• DCC – Duty Cycle Corrector
• ZQ Calibration
• PLL – Phase Locked Loop
• Bandgap References
• LDO / Voltage Regulators
• Clocking and high-speed interface circuits

Experience with DDR/LPDDR PHY, SerDes PHY or other high-speed mixed-signal IPs will be an added advantage.

Good to Have

• Experience with UVM-AMS methodology.
• Experience with RNM-based verification.
• Experience with mixed-mode simulation involving SPICE + RTL + behavioral models.
• Knowledge of PVT, Monte Carlo and corner‑based analog simulation.
• Experience with large-scale AMS regression environments.
• Exposure to advanced CMOS/FinFET technology nodes.Experience with AMS verification for DDR, SerDes or high-speed PHY IPs.
• Strong understanding of analog circuit behavior and transistor‑level simulation.