Analog/Mixed-Signal Verification- Lead

MediaTek; Bengaluru; On-site; INR 3,500,000 - 6,500,000; Full time

Job summary

MediaTek in Bengaluru seeks a Technical Lead for AMS Functional Verification of analog/mixed-signal IPs such as SERDES and sensors. You will lead a group spanning digital and analog DV teams, driving DV methodologies and end-to-end verification from spec to coverage closure.

The role emphasizes test bench development, coverage goals, and collaboration with global teams to ensure high-quality silicon products. Senior-level expertise in AMS DV is required.

Qualifications

• BS degree with 10+ years of relevant industry experience.
• MS degree with 8+ years of relevant industry experience.
• Proven expertise required for senior positions.

Responsibilities

• Contribute to DV process from specification to test plan and test bench development.
• Develop configurable test benches, drivers and checkers to meet functional and code coverage goals.
• Act as Technical Lead by guiding planning and resource allocation for project deliverables.
• Collaborate with global architecture, design, verification and post-silicon teams to address DV needs.
• Improve AMS DV processes for quality and efficiency.

Skills

UVM

Verilog

SystemVerilog

SVA

Analytical thinking

Leadership

Education

BS with 10+ years experience

MS with 8+ years experience

Tools

Perforce

ClearCase

Unix shell scripting

Python

Job description

Work on Analog/Mixed-Signal Functional Verification for Analog/Mixed-Signal IPs, such as SERDES, Sensors and beyond. The candidate will work as a Technical Lead for a group of engineers, who work with digital design, analog design, analog behavioral modeling and other design verification teams, apply and advance existing and evolving Digital and AMS Verification methodologies and processes, and contribute to the entire life cycle of AMS Functional Verification process, from understanding specification, test planning to coverage closure and post silicon debugging support, to ensure High Quality and High Efficiency of Pre-Si Verification Delivery towards high quality silicon products.

Skills/Experience:

• 10+ years of Experience.
• Quick learner with strong critical thinking and creative problem-solving skills.
• Solid knowledge in ASIC design process, digital design and UVM-based design verification methodologies.
• Proficient on using design and verification languages: UVM, Verilog, System Verilog, and System Verilog Assertions (SVA).
• Proficient on Design Verification tools and techniques, including test bench development, simulation, debugging and coverage closure, etc.
• Knowledge on Design Verification development process, from specification to test plan, to configurable test bench, drivers and checkers development, to test suite building to meet functional and code coverage goals,
• 3+ year Experience as Technical Lead of a Design Verification group/team is preferred.
• 3+ years ASIC functional verification hands-on work experience, preferably with some verification experience on analog mixed signal IPs or SERDES IPs, such as USB, UFS, PCIe, DDR-PHY, etc.
• Power-aware simulations and gate level simulations is a plus
• Scripting and automation skills: Unix/Linux shell programming, Perl, Python, Makefile, and revision management (e.g., Perforce, ClearCase, etc.) is a plus.
• Knowledge of Analog Mixed-Signal Design Fundamentals and analog behavioral modeling is a plus
• Familiar with programming languages: C, C++, and/or SystemC is a plus.

Responsibilities:

• Work in AMS IP Design Verification, in UVM-based verification environment.
• Work in DV process from specification to test plan, to configurable test bench, drivers and checkers development, to test suite building to meet functional and code coverage goals
• Act as Technical Lead of a Design Verification group/team by providing technical guidance, planning schedule and resource to meet requirement for project deliverables, fostering methodology advancement, and so on.
• Apply wide range of Digital and/or AMS DV skills to help and support AMS IP or Chip DV Teams to establish or enhance new or existing DV capabilities, including but not limited to developing scalable and portable Test bench, test cases, drivers, checkers, assertions and reference models, and running RTL and Gate Level simulations and reaching all coverage closures.
• Communicate and collaborate with global architecture, design, verification, and post-Silicon testing teams to address new needs or requirement on DV Support.
• Contribute to continuous improving on AMS DV process for better quality and efficiency through methodology and process improvements.

Education Requirements

• BS degree and a minimum of 10 years of relevant industry experience, or
• MS degree with a minimum of 8 years of relevant industry experience
• Senior positions to be offered to candidates with proven expertise in the relevant field